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67905540e8
Most of the Allwinner SoCs (at this time, all but the A10) also have a
High Speed timers that are not using the 24MHz oscillator as a source
but rather the AHB clock running much faster.
The IP is slightly different between the A10s/A13 and the one used in
the A20/A31, since the latter have 4 timers available, while the former
have only 2 of them.
[dlezcano] : Fixed conflict with b788beda "Order Kconfig options
alphabetically"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
23 lines
582 B
Plaintext
23 lines
582 B
Plaintext
Allwinner SoCs High Speed Timer Controller
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Required properties:
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- compatible : should be "allwinner,sun5i-a13-hstimer" or
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"allwinner,sun7i-a20-hstimer"
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
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one)
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- clocks: phandle to the source clock (usually the AHB clock)
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Example:
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timer@01c60000 {
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compatible = "allwinner,sun7i-a20-hstimer";
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reg = <0x01c60000 0x1000>;
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interrupts = <0 51 1>,
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<0 52 1>,
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<0 53 1>,
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<0 54 1>;
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clocks = <&ahb1_gates 19>;
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};
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