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acc0ccffec
This driver provides support for clock controller on Loongson-2 SoC, the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock, there are five independent PLLs inside, each of which PLL can provide up to three sets of frequency dependent clock outputs. Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20230323025229.2971-2-zhuyinbo@loongson.cn Signed-off-by: Stephen Boyd <sboyd@kernel.org>
342 lines
8.8 KiB
C
342 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Author: Yinbo Zhu <zhuyinbo@loongson.cn>
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* Copyright (C) 2022-2023 Loongson Technology Corporation Limited
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <dt-bindings/clock/loongson,ls2k-clk.h>
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#define LOONGSON2_PLL_MULT_SHIFT 32
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#define LOONGSON2_PLL_MULT_WIDTH 10
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#define LOONGSON2_PLL_DIV_SHIFT 26
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#define LOONGSON2_PLL_DIV_WIDTH 6
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#define LOONGSON2_APB_FREQSCALE_SHIFT 20
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#define LOONGSON2_APB_FREQSCALE_WIDTH 3
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#define LOONGSON2_USB_FREQSCALE_SHIFT 16
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#define LOONGSON2_USB_FREQSCALE_WIDTH 3
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#define LOONGSON2_SATA_FREQSCALE_SHIFT 12
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#define LOONGSON2_SATA_FREQSCALE_WIDTH 3
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#define LOONGSON2_BOOT_FREQSCALE_SHIFT 8
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#define LOONGSON2_BOOT_FREQSCALE_WIDTH 3
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static void __iomem *loongson2_pll_base;
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static const struct clk_parent_data pdata[] = {
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{ .fw_name = "ref_100m",},
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};
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static struct clk_hw *loongson2_clk_register(struct device *dev,
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const char *name,
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const char *parent_name,
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const struct clk_ops *ops,
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unsigned long flags)
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{
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int ret;
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struct clk_hw *hw;
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struct clk_init_data init;
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hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = ops;
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init.flags = flags;
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init.num_parents = 1;
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if (!parent_name)
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init.parent_data = pdata;
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else
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init.parent_names = &parent_name;
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hw->init = &init;
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ret = devm_clk_hw_register(dev, hw);
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if (ret)
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hw = ERR_PTR(ret);
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return hw;
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}
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static unsigned long loongson2_calc_pll_rate(int offset, unsigned long rate)
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{
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u64 val;
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u32 mult, div;
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val = readq(loongson2_pll_base + offset);
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mult = (val >> LOONGSON2_PLL_MULT_SHIFT) &
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clk_div_mask(LOONGSON2_PLL_MULT_WIDTH);
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div = (val >> LOONGSON2_PLL_DIV_SHIFT) &
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clk_div_mask(LOONGSON2_PLL_DIV_WIDTH);
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return div_u64((u64)rate * mult, div);
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}
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static unsigned long loongson2_node_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_pll_rate(0x0, parent_rate);
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}
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static const struct clk_ops loongson2_node_clk_ops = {
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.recalc_rate = loongson2_node_recalc_rate,
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};
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static unsigned long loongson2_ddr_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_pll_rate(0x10, parent_rate);
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}
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static const struct clk_ops loongson2_ddr_clk_ops = {
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.recalc_rate = loongson2_ddr_recalc_rate,
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};
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static unsigned long loongson2_dc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_pll_rate(0x20, parent_rate);
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}
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static const struct clk_ops loongson2_dc_clk_ops = {
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.recalc_rate = loongson2_dc_recalc_rate,
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};
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static unsigned long loongson2_pix0_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_pll_rate(0x30, parent_rate);
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}
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static const struct clk_ops loongson2_pix0_clk_ops = {
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.recalc_rate = loongson2_pix0_recalc_rate,
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};
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static unsigned long loongson2_pix1_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_pll_rate(0x40, parent_rate);
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}
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static const struct clk_ops loongson2_pix1_clk_ops = {
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.recalc_rate = loongson2_pix1_recalc_rate,
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};
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static unsigned long loongson2_calc_rate(unsigned long rate,
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int shift, int width)
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{
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u64 val;
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u32 mult;
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val = readq(loongson2_pll_base + 0x50);
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mult = (val >> shift) & clk_div_mask(width);
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return div_u64((u64)rate * (mult + 1), 8);
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}
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static unsigned long loongson2_boot_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_rate(parent_rate,
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LOONGSON2_BOOT_FREQSCALE_SHIFT,
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LOONGSON2_BOOT_FREQSCALE_WIDTH);
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}
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static const struct clk_ops loongson2_boot_clk_ops = {
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.recalc_rate = loongson2_boot_recalc_rate,
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};
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static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_rate(parent_rate,
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LOONGSON2_APB_FREQSCALE_SHIFT,
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LOONGSON2_APB_FREQSCALE_WIDTH);
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}
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static const struct clk_ops loongson2_apb_clk_ops = {
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.recalc_rate = loongson2_apb_recalc_rate,
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};
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static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_rate(parent_rate,
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LOONGSON2_USB_FREQSCALE_SHIFT,
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LOONGSON2_USB_FREQSCALE_WIDTH);
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}
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static const struct clk_ops loongson2_usb_clk_ops = {
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.recalc_rate = loongson2_usb_recalc_rate,
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};
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static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return loongson2_calc_rate(parent_rate,
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LOONGSON2_SATA_FREQSCALE_SHIFT,
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LOONGSON2_SATA_FREQSCALE_WIDTH);
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}
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static const struct clk_ops loongson2_sata_clk_ops = {
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.recalc_rate = loongson2_sata_recalc_rate,
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};
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static inline int loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count)
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{
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unsigned int i;
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for (i = 0; i < count; i++)
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if (IS_ERR(clks[i])) {
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pr_err("Loongson2 clk %u: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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return PTR_ERR(clks[i]);
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}
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return 0;
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}
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static int loongson2_clk_probe(struct platform_device *pdev)
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{
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int ret;
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struct clk_hw **hws;
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struct clk_hw_onecell_data *clk_hw_data;
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spinlock_t loongson2_clk_lock;
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struct device *dev = &pdev->dev;
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loongson2_pll_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(loongson2_pll_base))
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return PTR_ERR(loongson2_pll_base);
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clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, LOONGSON2_CLK_END),
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GFP_KERNEL);
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if (WARN_ON(!clk_hw_data))
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return -ENOMEM;
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clk_hw_data->num = LOONGSON2_CLK_END;
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hws = clk_hw_data->hws;
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hws[LOONGSON2_NODE_PLL] = loongson2_clk_register(dev, "node_pll",
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NULL,
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&loongson2_node_clk_ops, 0);
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hws[LOONGSON2_DDR_PLL] = loongson2_clk_register(dev, "ddr_pll",
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NULL,
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&loongson2_ddr_clk_ops, 0);
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hws[LOONGSON2_DC_PLL] = loongson2_clk_register(dev, "dc_pll",
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NULL,
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&loongson2_dc_clk_ops, 0);
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hws[LOONGSON2_PIX0_PLL] = loongson2_clk_register(dev, "pix0_pll",
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NULL,
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&loongson2_pix0_clk_ops, 0);
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hws[LOONGSON2_PIX1_PLL] = loongson2_clk_register(dev, "pix1_pll",
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NULL,
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&loongson2_pix1_clk_ops, 0);
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hws[LOONGSON2_BOOT_CLK] = loongson2_clk_register(dev, "boot",
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NULL,
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&loongson2_boot_clk_ops, 0);
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hws[LOONGSON2_NODE_CLK] = devm_clk_hw_register_divider(dev, "node",
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"node_pll", 0,
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loongson2_pll_base + 0x8, 0,
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6, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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/*
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* The hda clk divisor in the upper 32bits and the clk-prodiver
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* layer code doesn't support 64bit io operation thus a conversion
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* is required that subtract shift by 32 and add 4byte to the hda
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* address
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*/
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hws[LOONGSON2_HDA_CLK] = devm_clk_hw_register_divider(dev, "hda",
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"ddr_pll", 0,
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loongson2_pll_base + 0x22, 12,
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7, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_GPU_CLK] = devm_clk_hw_register_divider(dev, "gpu",
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"ddr_pll", 0,
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loongson2_pll_base + 0x18, 22,
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6, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_DDR_CLK] = devm_clk_hw_register_divider(dev, "ddr",
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"ddr_pll", 0,
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loongson2_pll_base + 0x18, 0,
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6, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_GMAC_CLK] = devm_clk_hw_register_divider(dev, "gmac",
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"dc_pll", 0,
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loongson2_pll_base + 0x28, 22,
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6, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_DC_CLK] = devm_clk_hw_register_divider(dev, "dc",
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"dc_pll", 0,
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loongson2_pll_base + 0x28, 0,
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6, CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_APB_CLK] = loongson2_clk_register(dev, "apb",
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"gmac",
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&loongson2_apb_clk_ops, 0);
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hws[LOONGSON2_USB_CLK] = loongson2_clk_register(dev, "usb",
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"gmac",
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&loongson2_usb_clk_ops, 0);
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hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(dev, "sata",
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"gmac",
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&loongson2_sata_clk_ops, 0);
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hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0",
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"pix0_pll", 0,
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loongson2_pll_base + 0x38, 0, 6,
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CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1",
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"pix1_pll", 0,
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loongson2_pll_base + 0x48, 0, 6,
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CLK_DIVIDER_ONE_BASED,
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&loongson2_clk_lock);
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ret = loongson2_check_clk_hws(hws, LOONGSON2_CLK_END);
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if (ret)
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return ret;
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_hw_data);
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}
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static const struct of_device_id loongson2_clk_match_table[] = {
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{ .compatible = "loongson,ls2k-clk" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, loongson2_clk_match_table);
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static struct platform_driver loongson2_clk_driver = {
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.probe = loongson2_clk_probe,
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.driver = {
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.name = "loongson2-clk",
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.of_match_table = loongson2_clk_match_table,
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},
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};
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module_platform_driver(loongson2_clk_driver);
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MODULE_DESCRIPTION("Loongson2 clock driver");
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MODULE_LICENSE("GPL");
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