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0bb66d3b6e
In some cases firmware brings up plls with different parameters than the ones noted in the rate table for the specific frequency. These firmware-selected parameters are worse than the tested ones in the pll rate tables but cannot be changed by a simple clk_set_rate call when the rate stays the same. Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback that checks the runtime-parameters against the matching rate table entry and adjusts them to the table-ones if necessary. If no rate table is set or the current rate does not match any rate-table entry no changes are made. Being able to limit this adjustment to specific plls is necessary to not touch the ones supplying core components like the apll and dpll supplying the armcores and dram. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kever Yang <kever.yang@rock-chips.com>
446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/div64.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "clk.h"
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#define PLL_MODE_MASK 0x3
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#define PLL_MODE_SLOW 0x0
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#define PLL_MODE_NORM 0x1
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#define PLL_MODE_DEEP 0x2
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struct rockchip_clk_pll {
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struct clk_hw hw;
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struct clk_mux pll_mux;
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const struct clk_ops *pll_mux_ops;
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struct notifier_block clk_nb;
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void __iomem *reg_base;
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int lock_offset;
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unsigned int lock_shift;
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enum rockchip_pll_type type;
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u8 flags;
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const struct rockchip_pll_rate_table *rate_table;
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unsigned int rate_count;
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spinlock_t *lock;
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};
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#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
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#define to_rockchip_clk_pll_nb(nb) \
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container_of(nb, struct rockchip_clk_pll, clk_nb)
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static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
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struct rockchip_clk_pll *pll, unsigned long rate)
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{
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const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
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int i;
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for (i = 0; i < pll->rate_count; i++) {
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if (rate == rate_table[i].rate)
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return &rate_table[i];
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}
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return NULL;
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}
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static long rockchip_pll_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
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int i;
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/* Assumming rate_table is in descending order */
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for (i = 0; i < pll->rate_count; i++) {
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if (drate >= rate_table[i].rate)
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return rate_table[i].rate;
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}
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/* return minimum supported value */
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return rate_table[i - 1].rate;
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}
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/*
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* Wait for the pll to reach the locked state.
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* The calling set_rate function is responsible for making sure the
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* grf regmap is available.
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*/
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static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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struct regmap *grf = rockchip_clk_get_grf();
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unsigned int val;
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int delay = 24000000, ret;
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while (delay > 0) {
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ret = regmap_read(grf, pll->lock_offset, &val);
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if (ret) {
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pr_err("%s: failed to read pll lock status: %d\n",
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__func__, ret);
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return ret;
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}
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if (val & BIT(pll->lock_shift))
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return 0;
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delay--;
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}
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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return -ETIMEDOUT;
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}
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/**
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* PLL used in RK3066, RK3188 and RK3288
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*/
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#define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
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#define RK3066_PLLCON(i) (i * 0x4)
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#define RK3066_PLLCON0_OD_MASK 0xf
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#define RK3066_PLLCON0_OD_SHIFT 0
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#define RK3066_PLLCON0_NR_MASK 0x3f
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#define RK3066_PLLCON0_NR_SHIFT 8
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#define RK3066_PLLCON1_NF_MASK 0x1fff
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#define RK3066_PLLCON1_NF_SHIFT 0
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#define RK3066_PLLCON2_BWADJ_MASK 0xfff
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#define RK3066_PLLCON2_BWADJ_SHIFT 0
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#define RK3066_PLLCON3_RESET (1 << 5)
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#define RK3066_PLLCON3_PWRDOWN (1 << 1)
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#define RK3066_PLLCON3_BYPASS (1 << 0)
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static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
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unsigned long prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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u64 nf, nr, no, rate64 = prate;
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u32 pllcon;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
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if (pllcon & RK3066_PLLCON3_BYPASS) {
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pr_debug("%s: pll %s is bypassed\n", __func__,
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__clk_get_name(hw->clk));
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return prate;
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}
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
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nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
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nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;
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no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;
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rate64 *= (nf + 1);
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do_div(rate64, nr + 1);
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do_div(rate64, no + 1);
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return (unsigned long)rate64;
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}
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static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long prate)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
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struct regmap *grf = rockchip_clk_get_grf();
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struct clk_mux *pll_mux = &pll->pll_mux;
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const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
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int rate_change_remuxed = 0;
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int cur_parent;
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int ret;
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if (IS_ERR(grf)) {
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pr_debug("%s: grf regmap not available, aborting rate change\n",
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__func__);
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return PTR_ERR(grf);
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}
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pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
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__func__, __clk_get_name(hw->clk), old_rate, drate, prate);
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/* Get required rate settings from table */
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rate = rockchip_get_pll_settings(pll, drate);
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if (!rate) {
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pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
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drate, __clk_get_name(hw->clk));
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return -EINVAL;
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}
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pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
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__func__, rate->rate, rate->nr, rate->no, rate->nf);
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cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
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if (cur_parent == PLL_MODE_NORM) {
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
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rate_change_remuxed = 1;
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}
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/* enter reset mode */
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writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
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pll->reg_base + RK3066_PLLCON(3));
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/* update pll values */
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writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
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RK3066_PLLCON0_NR_SHIFT) |
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HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
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RK3066_PLLCON0_OD_SHIFT),
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pll->reg_base + RK3066_PLLCON(0));
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writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
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RK3066_PLLCON1_NF_SHIFT),
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pll->reg_base + RK3066_PLLCON(1));
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writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK,
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RK3066_PLLCON2_BWADJ_SHIFT),
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pll->reg_base + RK3066_PLLCON(2));
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/* leave reset and wait the reset_delay */
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writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
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pll->reg_base + RK3066_PLLCON(3));
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udelay(RK3066_PLL_RESET_DELAY(rate->nr));
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/* wait for the pll to lock */
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ret = rockchip_pll_wait_lock(pll);
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if (ret) {
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pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
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__func__, old_rate);
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rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
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}
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if (rate_change_remuxed)
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pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
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return ret;
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}
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static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
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pll->reg_base + RK3066_PLLCON(3));
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return 0;
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}
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static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
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RK3066_PLLCON3_PWRDOWN, 0),
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pll->reg_base + RK3066_PLLCON(3));
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}
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static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
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return !(pllcon & RK3066_PLLCON3_PWRDOWN);
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}
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static void rockchip_rk3066_pll_init(struct clk_hw *hw)
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{
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struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
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const struct rockchip_pll_rate_table *rate;
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unsigned int nf, nr, no, bwadj;
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unsigned long drate;
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u32 pllcon;
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if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
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return;
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drate = __clk_get_rate(hw->clk);
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rate = rockchip_get_pll_settings(pll, drate);
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/* when no rate setting for the current rate, rely on clk_set_rate */
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if (!rate)
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return;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
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nr = ((pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK) + 1;
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no = ((pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK) + 1;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
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nf = ((pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK) + 1;
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pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));
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bwadj = (pllcon >> RK3066_PLLCON2_BWADJ_SHIFT) & RK3066_PLLCON2_BWADJ_MASK;
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pr_debug("%s: pll %s@%lu: nr (%d:%d); no (%d:%d); nf(%d:%d), bwadj(%d:%d)\n",
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__func__, __clk_get_name(hw->clk), drate, rate->nr, nr,
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rate->no, no, rate->nf, nf, rate->bwadj, bwadj);
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if (rate->nr != nr || rate->no != no || rate->nf != nf
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|| rate->bwadj != bwadj) {
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struct clk *parent = __clk_get_parent(hw->clk);
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unsigned long prate;
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if (!parent) {
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pr_warn("%s: parent of %s not available\n",
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__func__, __clk_get_name(hw->clk));
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return;
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}
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pr_debug("%s: pll %s: rate params do not match rate table, adjusting\n",
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__func__, __clk_get_name(hw->clk));
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prate = __clk_get_rate(parent);
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rockchip_rk3066_pll_set_rate(hw, drate, prate);
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}
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}
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static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
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.recalc_rate = rockchip_rk3066_pll_recalc_rate,
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.enable = rockchip_rk3066_pll_enable,
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.disable = rockchip_rk3066_pll_disable,
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.is_enabled = rockchip_rk3066_pll_is_enabled,
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};
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static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
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.recalc_rate = rockchip_rk3066_pll_recalc_rate,
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.round_rate = rockchip_pll_round_rate,
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.set_rate = rockchip_rk3066_pll_set_rate,
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.enable = rockchip_rk3066_pll_enable,
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.disable = rockchip_rk3066_pll_disable,
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.is_enabled = rockchip_rk3066_pll_is_enabled,
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.init = rockchip_rk3066_pll_init,
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};
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/*
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* Common registering of pll clocks
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*/
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struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
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const char *name, const char **parent_names, u8 num_parents,
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void __iomem *base, int con_offset, int grf_lock_offset,
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int lock_shift, int mode_offset, int mode_shift,
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struct rockchip_pll_rate_table *rate_table,
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u8 clk_pll_flags, spinlock_t *lock)
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{
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const char *pll_parents[3];
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struct clk_init_data init;
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struct rockchip_clk_pll *pll;
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struct clk_mux *pll_mux;
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struct clk *pll_clk, *mux_clk;
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char pll_name[20];
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if (num_parents != 2) {
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pr_err("%s: needs two parent clocks\n", __func__);
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return ERR_PTR(-EINVAL);
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}
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/* name the actual pll */
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snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = pll_name;
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/* keep all plls untouched for now */
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init.flags = CLK_IGNORE_UNUSED;
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init.parent_names = &parent_names[0];
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init.num_parents = 1;
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if (rate_table) {
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int len;
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/* find count of rates in rate_table */
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for (len = 0; rate_table[len].rate != 0; )
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len++;
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pll->rate_count = len;
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pll->rate_table = kmemdup(rate_table,
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pll->rate_count *
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sizeof(struct rockchip_pll_rate_table),
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GFP_KERNEL);
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WARN(!pll->rate_table,
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"%s: could not allocate rate table for %s\n",
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__func__, name);
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}
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switch (pll_type) {
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case pll_rk3066:
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if (!pll->rate_table)
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init.ops = &rockchip_rk3066_pll_clk_norate_ops;
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else
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init.ops = &rockchip_rk3066_pll_clk_ops;
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break;
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default:
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pr_warn("%s: Unknown pll type for pll clk %s\n",
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__func__, name);
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}
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pll->hw.init = &init;
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pll->type = pll_type;
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pll->reg_base = base + con_offset;
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pll->lock_offset = grf_lock_offset;
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pll->lock_shift = lock_shift;
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pll->flags = clk_pll_flags;
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pll->lock = lock;
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/* create the mux on top of the real pll */
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pll->pll_mux_ops = &clk_mux_ops;
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pll_mux = &pll->pll_mux;
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pll_mux->reg = base + mode_offset;
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pll_mux->shift = mode_shift;
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pll_mux->mask = PLL_MODE_MASK;
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pll_mux->flags = 0;
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pll_mux->lock = lock;
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pll_mux->hw.init = &init;
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if (pll_type == pll_rk3066)
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pll_mux->flags |= CLK_MUX_HIWORD_MASK;
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pll_clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(pll_clk)) {
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pr_err("%s: failed to register pll clock %s : %ld\n",
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__func__, name, PTR_ERR(pll_clk));
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mux_clk = pll_clk;
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goto err_pll;
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}
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/* the actual muxing is xin24m, pll-output, xin32k */
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pll_parents[0] = parent_names[0];
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pll_parents[1] = pll_name;
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pll_parents[2] = parent_names[1];
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.ops = pll->pll_mux_ops;
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init.parent_names = pll_parents;
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init.num_parents = ARRAY_SIZE(pll_parents);
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mux_clk = clk_register(NULL, &pll_mux->hw);
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if (IS_ERR(mux_clk))
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goto err_mux;
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return mux_clk;
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err_mux:
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clk_unregister(pll_clk);
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err_pll:
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kfree(pll);
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return mux_clk;
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}
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