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In order to support DT for mmp SOC clocks, it defines some basic APIs which are shared by all mmp SOC clock units. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
240 lines
5.5 KiB
C
240 lines
5.5 KiB
C
#ifndef __MACH_MMP_CLK_H
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#define __MACH_MMP_CLK_H
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#define APBC_NO_BUS_CTRL BIT(0)
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#define APBC_POWER_CTRL BIT(1)
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/* Clock type "factor" */
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struct mmp_clk_factor_masks {
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unsigned int factor;
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unsigned int num_mask;
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unsigned int den_mask;
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unsigned int num_shift;
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unsigned int den_shift;
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};
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struct mmp_clk_factor_tbl {
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unsigned int num;
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unsigned int den;
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};
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struct mmp_clk_factor {
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struct clk_hw hw;
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void __iomem *base;
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struct mmp_clk_factor_masks *masks;
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struct mmp_clk_factor_tbl *ftbl;
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unsigned int ftbl_cnt;
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spinlock_t *lock;
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};
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extern struct clk *mmp_clk_register_factor(const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *base, struct mmp_clk_factor_masks *masks,
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struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
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spinlock_t *lock);
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/* Clock type "mix" */
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#define MMP_CLK_BITS_MASK(width, shift) \
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(((1 << (width)) - 1) << (shift))
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#define MMP_CLK_BITS_GET_VAL(data, width, shift) \
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((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
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#define MMP_CLK_BITS_SET_VAL(val, width, shift) \
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(((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
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enum {
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MMP_CLK_MIX_TYPE_V1,
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MMP_CLK_MIX_TYPE_V2,
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MMP_CLK_MIX_TYPE_V3,
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};
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/* The register layout */
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struct mmp_clk_mix_reg_info {
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void __iomem *reg_clk_ctrl;
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void __iomem *reg_clk_sel;
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u8 width_div;
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u8 shift_div;
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u8 width_mux;
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u8 shift_mux;
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u8 bit_fc;
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};
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/* The suggested clock table from user. */
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struct mmp_clk_mix_clk_table {
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unsigned long rate;
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u8 parent_index;
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unsigned int divisor;
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unsigned int valid;
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};
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struct mmp_clk_mix_config {
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struct mmp_clk_mix_reg_info reg_info;
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struct mmp_clk_mix_clk_table *table;
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unsigned int table_size;
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u32 *mux_table;
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struct clk_div_table *div_table;
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u8 div_flags;
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u8 mux_flags;
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};
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struct mmp_clk_mix {
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struct clk_hw hw;
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struct mmp_clk_mix_reg_info reg_info;
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struct mmp_clk_mix_clk_table *table;
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u32 *mux_table;
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struct clk_div_table *div_table;
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unsigned int table_size;
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u8 div_flags;
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u8 mux_flags;
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unsigned int type;
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spinlock_t *lock;
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};
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extern const struct clk_ops mmp_clk_mix_ops;
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extern struct clk *mmp_clk_register_mix(struct device *dev,
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const char *name,
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const char **parent_names,
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u8 num_parents,
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unsigned long flags,
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struct mmp_clk_mix_config *config,
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spinlock_t *lock);
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/* Clock type "gate". MMP private gate */
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#define MMP_CLK_GATE_NEED_DELAY BIT(0)
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struct mmp_clk_gate {
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struct clk_hw hw;
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void __iomem *reg;
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u32 mask;
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u32 val_enable;
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u32 val_disable;
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unsigned int flags;
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spinlock_t *lock;
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};
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extern const struct clk_ops mmp_clk_gate_ops;
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extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u32 mask, u32 val_enable,
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u32 val_disable, unsigned int gate_flags,
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spinlock_t *lock);
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extern struct clk *mmp_clk_register_pll2(const char *name,
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const char *parent_name, unsigned long flags);
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extern struct clk *mmp_clk_register_apbc(const char *name,
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const char *parent_name, void __iomem *base,
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unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
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extern struct clk *mmp_clk_register_apmu(const char *name,
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const char *parent_name, void __iomem *base, u32 enable_mask,
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spinlock_t *lock);
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struct mmp_clk_unit {
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unsigned int nr_clks;
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struct clk **clk_table;
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struct clk_onecell_data clk_data;
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};
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struct mmp_param_fixed_rate_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long fixed_rate;
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};
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void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_rate_clk *clks,
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int size);
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struct mmp_param_fixed_factor_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long mult;
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unsigned long div;
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unsigned long flags;
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};
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void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
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struct mmp_param_fixed_factor_clk *clks,
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int size);
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struct mmp_param_general_gate_clk {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 bit_idx;
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u8 gate_flags;
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spinlock_t *lock;
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};
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void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_general_gate_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_gate_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u32 mask;
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u32 val_enable;
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u32 val_disable;
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unsigned int gate_flags;
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spinlock_t *lock;
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};
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void mmp_register_gate_clks(struct mmp_clk_unit *unit,
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struct mmp_param_gate_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_mux_clk {
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unsigned int id;
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char *name;
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const char **parent_name;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 mux_flags;
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spinlock_t *lock;
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};
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void mmp_register_mux_clks(struct mmp_clk_unit *unit,
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struct mmp_param_mux_clk *clks,
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void __iomem *base, int size);
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struct mmp_param_div_clk {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 div_flags;
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spinlock_t *lock;
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};
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void mmp_register_div_clks(struct mmp_clk_unit *unit,
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struct mmp_param_div_clk *clks,
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void __iomem *base, int size);
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#define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
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{ \
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.width_div = (w_d), \
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.shift_div = (s_d), \
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.width_mux = (w_m), \
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.shift_mux = (s_m), \
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.bit_fc = (fc), \
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}
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void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
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int nr_clks);
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void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
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struct clk *clk);
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#endif
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