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bcc5fd49a0
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
419 lines
9.8 KiB
C
419 lines
9.8 KiB
C
/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <asm/proc-fns.h>
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#include "pmc.h"
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void __iomem *at91_pmc_base;
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EXPORT_SYMBOL_GPL(at91_pmc_base);
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void at91sam9_idle(void)
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{
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at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
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cpu_do_idle();
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}
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int of_at91_get_clk_range(struct device_node *np, const char *propname,
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struct clk_range *range)
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{
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u32 min, max;
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int ret;
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ret = of_property_read_u32_index(np, propname, 0, &min);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(np, propname, 1, &max);
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if (ret)
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return ret;
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if (range) {
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range->min = min;
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range->max = max;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
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static void pmc_irq_mask(struct irq_data *d)
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{
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struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
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pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq);
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}
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static void pmc_irq_unmask(struct irq_data *d)
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{
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struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
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pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq);
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}
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static int pmc_irq_set_type(struct irq_data *d, unsigned type)
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{
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if (type != IRQ_TYPE_LEVEL_HIGH) {
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pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n");
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip pmc_irq = {
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.name = "PMC",
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.irq_disable = pmc_irq_mask,
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.irq_mask = pmc_irq_mask,
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.irq_unmask = pmc_irq_unmask,
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.irq_set_type = pmc_irq_set_type,
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};
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static struct lock_class_key pmc_lock_class;
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static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct at91_pmc *pmc = h->host_data;
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irq_set_lockdep_class(virq, &pmc_lock_class);
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irq_set_chip_and_handler(virq, &pmc_irq,
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handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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irq_set_chip_data(virq, pmc);
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return 0;
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}
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static int pmc_irq_domain_xlate(struct irq_domain *d,
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struct device_node *ctrlr,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_type)
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{
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struct at91_pmc *pmc = d->host_data;
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const struct at91_pmc_caps *caps = pmc->caps;
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if (WARN_ON(intsize < 1))
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return -EINVAL;
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*out_hwirq = intspec[0];
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if (!(caps->available_irqs & (1 << *out_hwirq)))
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return -EINVAL;
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*out_type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static struct irq_domain_ops pmc_irq_ops = {
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.map = pmc_irq_map,
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.xlate = pmc_irq_domain_xlate,
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};
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static irqreturn_t pmc_irq_handler(int irq, void *data)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)data;
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unsigned long sr;
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int n;
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sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR);
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if (!sr)
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return IRQ_NONE;
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for_each_set_bit(n, &sr, BITS_PER_LONG)
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generic_handle_irq(irq_find_mapping(pmc->irqdomain, n));
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return IRQ_HANDLED;
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}
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static const struct at91_pmc_caps at91rm9200_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
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AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
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AT91_PMC_PCK3RDY,
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};
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static const struct at91_pmc_caps at91sam9260_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
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AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY,
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};
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static const struct at91_pmc_caps at91sam9g45_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
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AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY,
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};
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static const struct at91_pmc_caps at91sam9n12_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
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AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
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AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
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};
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static const struct at91_pmc_caps at91sam9x5_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
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AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
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AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
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};
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static const struct at91_pmc_caps sama5d3_caps = {
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.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
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AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
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AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
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AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS |
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AT91_PMC_CFDEV,
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};
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static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
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void __iomem *regbase, int virq,
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const struct at91_pmc_caps *caps)
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{
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struct at91_pmc *pmc;
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if (!regbase || !virq || !caps)
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return NULL;
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at91_pmc_base = regbase;
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pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
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if (!pmc)
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return NULL;
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spin_lock_init(&pmc->lock);
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pmc->regbase = regbase;
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pmc->virq = virq;
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pmc->caps = caps;
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pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
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if (!pmc->irqdomain)
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goto out_free_pmc;
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pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
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if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc))
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goto out_remove_irqdomain;
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return pmc;
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out_remove_irqdomain:
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irq_domain_remove(pmc->irqdomain);
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out_free_pmc:
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kfree(pmc);
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return NULL;
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}
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static const struct of_device_id pmc_clk_ids[] __initconst = {
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/* Slow oscillator */
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{
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.compatible = "atmel,at91sam9260-clk-slow",
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.data = of_at91sam9260_clk_slow_setup,
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},
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/* Main clock */
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{
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.compatible = "atmel,at91rm9200-clk-main-osc",
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.data = of_at91rm9200_clk_main_osc_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-main-rc-osc",
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.data = of_at91sam9x5_clk_main_rc_osc_setup,
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},
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{
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.compatible = "atmel,at91rm9200-clk-main",
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.data = of_at91rm9200_clk_main_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-main",
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.data = of_at91sam9x5_clk_main_setup,
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},
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/* PLL clocks */
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{
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.compatible = "atmel,at91rm9200-clk-pll",
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.data = of_at91rm9200_clk_pll_setup,
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},
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{
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.compatible = "atmel,at91sam9g45-clk-pll",
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.data = of_at91sam9g45_clk_pll_setup,
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},
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{
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.compatible = "atmel,at91sam9g20-clk-pllb",
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.data = of_at91sam9g20_clk_pllb_setup,
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},
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{
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.compatible = "atmel,sama5d3-clk-pll",
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.data = of_sama5d3_clk_pll_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-plldiv",
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.data = of_at91sam9x5_clk_plldiv_setup,
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},
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/* Master clock */
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{
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.compatible = "atmel,at91rm9200-clk-master",
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.data = of_at91rm9200_clk_master_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-master",
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.data = of_at91sam9x5_clk_master_setup,
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},
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/* System clocks */
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{
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.compatible = "atmel,at91rm9200-clk-system",
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.data = of_at91rm9200_clk_sys_setup,
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},
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/* Peripheral clocks */
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{
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.compatible = "atmel,at91rm9200-clk-peripheral",
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.data = of_at91rm9200_clk_periph_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-peripheral",
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.data = of_at91sam9x5_clk_periph_setup,
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},
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/* Programmable clocks */
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{
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.compatible = "atmel,at91rm9200-clk-programmable",
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.data = of_at91rm9200_clk_prog_setup,
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},
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{
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.compatible = "atmel,at91sam9g45-clk-programmable",
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.data = of_at91sam9g45_clk_prog_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-programmable",
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.data = of_at91sam9x5_clk_prog_setup,
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},
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/* UTMI clock */
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#if defined(CONFIG_HAVE_AT91_UTMI)
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{
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.compatible = "atmel,at91sam9x5-clk-utmi",
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.data = of_at91sam9x5_clk_utmi_setup,
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},
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#endif
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/* USB clock */
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#if defined(CONFIG_HAVE_AT91_USB_CLK)
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{
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.compatible = "atmel,at91rm9200-clk-usb",
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.data = of_at91rm9200_clk_usb_setup,
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},
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{
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.compatible = "atmel,at91sam9x5-clk-usb",
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.data = of_at91sam9x5_clk_usb_setup,
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},
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{
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.compatible = "atmel,at91sam9n12-clk-usb",
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.data = of_at91sam9n12_clk_usb_setup,
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},
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#endif
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/* SMD clock */
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#if defined(CONFIG_HAVE_AT91_SMD)
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{
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.compatible = "atmel,at91sam9x5-clk-smd",
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.data = of_at91sam9x5_clk_smd_setup,
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},
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#endif
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#if defined(CONFIG_HAVE_AT91_H32MX)
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{
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.compatible = "atmel,sama5d4-clk-h32mx",
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.data = of_sama5d4_clk_h32mx_setup,
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},
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#endif
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{ /*sentinel*/ }
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};
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static void __init of_at91_pmc_setup(struct device_node *np,
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const struct at91_pmc_caps *caps)
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{
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struct at91_pmc *pmc;
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struct device_node *childnp;
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void (*clk_setup)(struct device_node *, struct at91_pmc *);
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const struct of_device_id *clk_id;
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void __iomem *regbase = of_iomap(np, 0);
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int virq;
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if (!regbase)
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return;
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virq = irq_of_parse_and_map(np, 0);
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if (!virq)
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return;
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pmc = at91_pmc_init(np, regbase, virq, caps);
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if (!pmc)
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return;
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for_each_child_of_node(np, childnp) {
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clk_id = of_match_node(pmc_clk_ids, childnp);
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if (!clk_id)
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continue;
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clk_setup = clk_id->data;
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clk_setup(childnp, pmc);
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}
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}
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static void __init of_at91rm9200_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &at91rm9200_caps);
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}
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CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc",
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of_at91rm9200_pmc_setup);
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static void __init of_at91sam9260_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &at91sam9260_caps);
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}
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CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc",
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of_at91sam9260_pmc_setup);
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static void __init of_at91sam9g45_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &at91sam9g45_caps);
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}
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CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc",
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of_at91sam9g45_pmc_setup);
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static void __init of_at91sam9n12_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &at91sam9n12_caps);
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}
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CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc",
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of_at91sam9n12_pmc_setup);
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static void __init of_at91sam9x5_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &at91sam9x5_caps);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc",
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of_at91sam9x5_pmc_setup);
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static void __init of_sama5d3_pmc_setup(struct device_node *np)
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{
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of_at91_pmc_setup(np, &sama5d3_caps);
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}
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CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc",
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of_sama5d3_pmc_setup);
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