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91bbefe6b0
MIPS is interesting and has hardware variants that reorder over ll/sc as well as those that do not. Implement the 2 new barrier functions as per the old barriers. Signed-off-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-9ph49jbae3hol9v721sbc2g6@git.kernel.org Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Maciej W. Rozycki" <macro@codesourcery.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Will Deacon <will.deacon@arm.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
165 lines
3.3 KiB
C
165 lines
3.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Code to handle x86 style IRQs plus some generic interrupt stuff.
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*
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* Copyright (C) 1992 Linus Torvalds
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* Copyright (C) 1994 - 2000 Ralf Baechle
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/proc_fs.h>
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#include <linux/mm.h>
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#include <linux/random.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/kallsyms.h>
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#include <linux/kgdb.h>
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#include <linux/ftrace.h>
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#include <linux/atomic.h>
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#include <asm/uaccess.h>
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#ifdef CONFIG_KGDB
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int kgdb_early_setup;
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#endif
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static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
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int allocate_irqno(void)
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{
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int irq;
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again:
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irq = find_first_zero_bit(irq_map, NR_IRQS);
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if (irq >= NR_IRQS)
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return -ENOSPC;
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if (test_and_set_bit(irq, irq_map))
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goto again;
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return irq;
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}
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/*
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* Allocate the 16 legacy interrupts for i8259 devices. This happens early
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* in the kernel initialization so treating allocation failure as BUG() is
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* ok.
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*/
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void __init alloc_legacy_irqno(void)
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{
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int i;
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for (i = 0; i <= 16; i++)
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BUG_ON(test_and_set_bit(i, irq_map));
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}
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void free_irqno(unsigned int irq)
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{
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smp_mb__before_atomic();
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clear_bit(irq, irq_map);
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smp_mb__after_atomic();
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}
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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smtc_im_ack_irq(irq);
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printk("unexpected IRQ # %d\n", irq);
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}
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atomic_t irq_err_count;
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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return 0;
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}
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asmlinkage void spurious_interrupt(void)
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{
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atomic_inc(&irq_err_count);
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}
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void __init init_IRQ(void)
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{
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int i;
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#ifdef CONFIG_KGDB
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if (kgdb_early_setup)
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return;
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#endif
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for (i = 0; i < NR_IRQS; i++)
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irq_set_noprobe(i);
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arch_init_irq();
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#ifdef CONFIG_KGDB
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if (!kgdb_early_setup)
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kgdb_early_setup = 1;
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#endif
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}
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#ifdef DEBUG_STACKOVERFLOW
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static inline void check_stack_overflow(void)
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{
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unsigned long sp;
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__asm__ __volatile__("move %0, $sp" : "=r" (sp));
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sp &= THREAD_MASK;
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/*
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* Check for stack overflow: is there less than STACK_WARN free?
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* STACK_WARN is defined as 1/8 of THREAD_SIZE by default.
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*/
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if (unlikely(sp < (sizeof(struct thread_info) + STACK_WARN))) {
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printk("do_IRQ: stack overflow: %ld\n",
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sp - sizeof(struct thread_info));
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dump_stack();
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}
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}
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#else
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static inline void check_stack_overflow(void) {}
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#endif
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/*
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* do_IRQ handles all normal device IRQ's (the special
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* SMP cross-CPU interrupts have their own specific
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* handlers).
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*/
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void __irq_entry do_IRQ(unsigned int irq)
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{
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irq_enter();
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check_stack_overflow();
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if (!smtc_handle_on_other_cpu(irq))
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generic_handle_irq(irq);
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irq_exit();
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}
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#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
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/*
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* To avoid inefficient and in some cases pathological re-checking of
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* IRQ affinity, we have this variant that skips the affinity check.
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*/
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void __irq_entry do_IRQ_no_affinity(unsigned int irq)
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{
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irq_enter();
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smtc_im_backstop(irq);
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generic_handle_irq(irq);
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irq_exit();
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}
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#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
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