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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* Support for IBM PPC 405EP evaluation board (Bubinga).
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*
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* Author: SAW (IBM), derived from walnut.h.
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* Maintained by MontaVista Software <source@mvista.com>
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*
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* 2003 (c) MontaVista Softare Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __BUBINGA_H__
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#define __BUBINGA_H__
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/* 405EP */
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#include <platforms/4xx/ibm405ep.h>
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#ifndef __ASSEMBLY__
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/*
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* Data structure defining board information maintained by the boot
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* ROM on IBM's evaluation board. An effort has been made to
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* keep the field names consistent with the 8xx 'bd_t' board info
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* structures.
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*/
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typedef struct board_info {
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unsigned char bi_s_version[4]; /* Version of this structure */
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unsigned char bi_r_version[30]; /* Version of the IBM ROM */
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unsigned int bi_memsize; /* DRAM installed, in bytes */
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unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */
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unsigned int bi_intfreq; /* Processor speed, in Hz */
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unsigned int bi_busfreq; /* PLB Bus speed, in Hz */
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unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
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unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */
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unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */
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} bd_t;
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/* Some 4xx parts use a different timebase frequency from the internal clock.
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*/
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#define bi_tbfreq bi_intfreq
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/* Memory map for the Bubinga board.
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* Generic 4xx plus RTC.
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*/
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extern void *bubinga_rtc_base;
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#define BUBINGA_RTC_PADDR ((uint)0xf0000000)
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#define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR
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#define BUBINGA_RTC_SIZE ((uint)8*1024)
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/* The UART clock is based off an internal clock -
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* define BASE_BAUD based on the internal clock and divider(s).
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* Since BASE_BAUD must be a constant, we will initialize it
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* using clock/divider values which OpenBIOS initializes
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* for typical configurations at various CPU speeds.
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* The base baud is calculated as (FWDA / EXT UART DIV / 16)
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*/
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#define BASE_BAUD 0
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#define BUBINGA_FPGA_BASE 0xF0300000
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#define PPC4xx_MACHINE_NAME "IBM Bubinga"
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#endif /* !__ASSEMBLY__ */
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#endif /* __BUBINGA_H__ */
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#endif /* __KERNEL__ */
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