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f8b52dd50c
Some i.MX SoCs have GPIO clock gate in CCM, accessing GPIO registers needs to enable GPIO clock gate first, i.MX GPIO driver will enable clock gate if there is clock property in GPIO node of dtb, add optional property to i.MX GPIO binding doc. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
* Freescale i.MX/MXC GPIO controller
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Required properties:
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- compatible : Should be "fsl,<soc>-gpio"
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- reg : Address and length of the register set for the device
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- interrupts : Should be the port interrupt shared by all 32 pins, if
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one number. If two numbers, the first one is the interrupt shared
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by low 16 pins and the second one is for high 16 pins.
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- gpio-controller : Marks the device node as a gpio controller.
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells : Should be 2. The first cell is the GPIO number.
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The second cell bits[3:0] is used to specify trigger type and level flags:
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1 = low-to-high edge triggered.
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2 = high-to-low edge triggered.
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4 = active high level-sensitive.
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8 = active low level-sensitive.
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Optional properties:
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- clocks: the clock for clocking the GPIO silicon
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Example:
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gpio0: gpio@73f84000 {
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compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
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reg = <0x73f84000 0x4000>;
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interrupts = <50 51>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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