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According to CY7C67300 specification HPI read and write cycle duration
Tcyc must be at least 6T long, where T is 1/48MHz, which is 125ns.
Without this delay fast host processor cannot write to chip registers.
Add proper ndelay to hpi_{read,write}_reg.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Peter Korsgaard <peter@korsgaard.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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| .. | ||
| c67x00-drv.c | ||
| c67x00-hcd.c | ||
| c67x00-hcd.h | ||
| c67x00-ll-hpi.c | ||
| c67x00-sched.c | ||
| c67x00.h | ||
| Makefile | ||