mirror of
https://github.com/torvalds/linux.git
synced 2024-11-08 05:01:48 +00:00
ce5ea9f376
Making CACHE_L2X0 depend on (huge list of MACH_ and ARCH_ configs)
is bothersome to maintain and likely to lead to merge conflicts.
This patch moves the knowledge of which platforms have a L2x0 or
PL310 cache controller to the individual machines. To enable this,
a new MIGHT_HAVE_CACHE_L2X0 config option is introduced to allow
machines to indicate that they may have such a cache controller
independently of each other.
Boards/SoCs which cannot reliably operate without the L2 cache
controller support will need to select CACHE_L2X0 directly from
their own Kconfigs instead. This applies to some TrustZone-enabled
boards where Linux runs in the Normal World, for example.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Anton Vorontsov <cbouatmailru@gmail.com>
(for cns3xxx)
Acked-by: Tony Lindgren <tony@atomide.com>
(for omap)
Acked-by: Shawn Guo <shawn.guo@linaro.org>
(for imx)
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
(for exynos)
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
(for imx)
Acked-by: Olof Johansson <olof@lixom.net>
(for tegra)
111 lines
2.5 KiB
Plaintext
111 lines
2.5 KiB
Plaintext
if ARCH_MXC
|
|
|
|
source "arch/arm/plat-mxc/devices/Kconfig"
|
|
|
|
menu "Freescale MXC Implementations"
|
|
|
|
choice
|
|
prompt "Freescale CPU family:"
|
|
default ARCH_IMX_V6_V7
|
|
|
|
config ARCH_IMX_V4_V5
|
|
bool "i.MX1, i.MX21, i.MX25, i.MX27"
|
|
select AUTO_ZRELADDR if !ZBOOT_ROM
|
|
select ARM_PATCH_PHYS_VIRT
|
|
help
|
|
This enables support for systems based on the Freescale i.MX ARMv4
|
|
and ARMv5 SoCs
|
|
|
|
config ARCH_IMX_V6_V7
|
|
bool "i.MX3, i.MX6"
|
|
select AUTO_ZRELADDR if !ZBOOT_ROM
|
|
select ARM_PATCH_PHYS_VIRT
|
|
select MIGHT_HAVE_CACHE_L2X0
|
|
help
|
|
This enables support for systems based on the Freescale i.MX3 and i.MX6
|
|
family.
|
|
|
|
config ARCH_MX5
|
|
bool "i.MX50, i.MX51, i.MX53"
|
|
select AUTO_ZRELADDR if !ZBOOT_ROM
|
|
select ARM_PATCH_PHYS_VIRT
|
|
help
|
|
This enables support for machines using Freescale's i.MX50 and i.MX53
|
|
processors.
|
|
|
|
endchoice
|
|
|
|
source "arch/arm/mach-imx/Kconfig"
|
|
source "arch/arm/mach-mx5/Kconfig"
|
|
|
|
endmenu
|
|
|
|
config MXC_IRQ_PRIOR
|
|
bool "Use IRQ priority"
|
|
help
|
|
Select this if you want to use prioritized IRQ handling.
|
|
This feature prevents higher priority ISR to be interrupted
|
|
by lower priority IRQ even IRQF_DISABLED flag is not set.
|
|
This may be useful in embedded applications, where are strong
|
|
requirements for timing.
|
|
Say N here, unless you have a specialized requirement.
|
|
|
|
config MXC_TZIC
|
|
bool
|
|
|
|
config MXC_AVIC
|
|
bool
|
|
|
|
config MXC_PWM
|
|
tristate "Enable PWM driver"
|
|
select HAVE_PWM
|
|
help
|
|
Enable support for the i.MX PWM controller(s).
|
|
|
|
config MXC_DEBUG_BOARD
|
|
bool "Enable MXC debug board(for 3-stack)"
|
|
help
|
|
The debug board is an integral part of the MXC 3-stack(PDK)
|
|
platforms, it can be attached or removed from the peripheral
|
|
board. On debug board, several debug devices(ethernet, UART,
|
|
buttons, LEDs and JTAG) are implemented. Between the MCU and
|
|
these devices, a CPLD is added as a bridge which performs
|
|
data/address de-multiplexing and decode, signal level shift,
|
|
interrupt control and various board functions.
|
|
|
|
config HAVE_EPIT
|
|
bool
|
|
|
|
config MXC_USE_EPIT
|
|
bool "Use EPIT instead of GPT"
|
|
depends on HAVE_EPIT
|
|
help
|
|
Use EPIT as the system timer on systems that have it. Normally you
|
|
don't have a reason to do so as the EPIT has the same features and
|
|
uses the same clocks as the GPT. Anyway, on some systems the GPT
|
|
may be in use for other purposes.
|
|
|
|
config MXC_ULPI
|
|
bool
|
|
|
|
config ARCH_HAS_RNGA
|
|
bool
|
|
|
|
config IMX_HAVE_IOMUX_V1
|
|
bool
|
|
|
|
config ARCH_MXC_IOMUX_V3
|
|
bool
|
|
|
|
config ARCH_MXC_AUDMUX_V1
|
|
bool
|
|
|
|
config ARCH_MXC_AUDMUX_V2
|
|
bool
|
|
|
|
config IRAM_ALLOC
|
|
bool
|
|
select GENERIC_ALLOCATOR
|
|
|
|
endif
|