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0b17fc08e3
Calculate GPU offset within vmwgfx driver itself without depending on bo->offset. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/372933/ Signed-off-by: Christian König <christian.koenig@amd.com>
692 lines
19 KiB
C
692 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/**************************************************************************
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*
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* Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include <linux/sched/signal.h>
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#include <drm/ttm/ttm_placement.h>
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#include "vmwgfx_drv.h"
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struct vmw_temp_set_context {
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SVGA3dCmdHeader header;
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SVGA3dCmdDXTempSetContext body;
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};
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bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t fifo_min, hwversion;
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const struct vmw_fifo_state *fifo = &dev_priv->fifo;
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if (!(dev_priv->capabilities & SVGA_CAP_3D))
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return false;
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if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
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uint32_t result;
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if (!dev_priv->has_mob)
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return false;
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spin_lock(&dev_priv->cap_lock);
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vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
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result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
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spin_unlock(&dev_priv->cap_lock);
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return (result != 0);
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}
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if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
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return false;
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fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
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if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
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return false;
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hwversion = vmw_mmio_read(fifo_mem +
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((fifo->capabilities &
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SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
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SVGA_FIFO_3D_HWVERSION_REVISED :
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SVGA_FIFO_3D_HWVERSION));
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if (hwversion == 0)
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return false;
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if (hwversion < SVGA3D_HWVERSION_WS8_B1)
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return false;
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/* Legacy Display Unit does not support surfaces */
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if (dev_priv->active_display_unit == vmw_du_legacy)
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return false;
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return true;
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}
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bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t caps;
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if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
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return false;
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caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
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if (caps & SVGA_FIFO_CAP_PITCHLOCK)
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return true;
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return false;
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}
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int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t max;
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uint32_t min;
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fifo->dx = false;
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fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
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fifo->static_buffer = vmalloc(fifo->static_buffer_size);
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if (unlikely(fifo->static_buffer == NULL))
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return -ENOMEM;
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fifo->dynamic_buffer = NULL;
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fifo->reserved_size = 0;
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fifo->using_bounce_buffer = false;
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mutex_init(&fifo->fifo_mutex);
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init_rwsem(&fifo->rwsem);
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DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
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DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
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DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
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dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
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dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
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dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
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vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
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SVGA_REG_ENABLE_HIDE);
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vmw_write(dev_priv, SVGA_REG_TRACES, 0);
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min = 4;
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if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
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min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
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min <<= 2;
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if (min < PAGE_SIZE)
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min = PAGE_SIZE;
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vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN);
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vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
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wmb();
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vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
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vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP);
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vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY);
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mb();
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vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
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max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
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min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
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fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES);
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DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
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(unsigned int) max,
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(unsigned int) min,
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(unsigned int) fifo->capabilities);
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atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
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vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
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vmw_marker_queue_init(&fifo->marker_queue);
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return 0;
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}
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void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
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vmw_write(dev_priv, SVGA_REG_SYNC, reason);
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}
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void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
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while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
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;
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dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE);
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vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
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dev_priv->config_done_state);
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vmw_write(dev_priv, SVGA_REG_ENABLE,
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dev_priv->enable_state);
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vmw_write(dev_priv, SVGA_REG_TRACES,
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dev_priv->traces_state);
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vmw_marker_queue_takedown(&fifo->marker_queue);
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if (likely(fifo->static_buffer != NULL)) {
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vfree(fifo->static_buffer);
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fifo->static_buffer = NULL;
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}
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if (likely(fifo->dynamic_buffer != NULL)) {
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vfree(fifo->dynamic_buffer);
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fifo->dynamic_buffer = NULL;
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}
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}
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static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
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{
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
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uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
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uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
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uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
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return ((max - next_cmd) + (stop - min) <= bytes);
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}
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static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
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uint32_t bytes, bool interruptible,
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unsigned long timeout)
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{
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int ret = 0;
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unsigned long end_jiffies = jiffies + timeout;
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DEFINE_WAIT(__wait);
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DRM_INFO("Fifo wait noirq.\n");
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for (;;) {
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prepare_to_wait(&dev_priv->fifo_queue, &__wait,
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(interruptible) ?
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TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
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if (!vmw_fifo_is_full(dev_priv, bytes))
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break;
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if (time_after_eq(jiffies, end_jiffies)) {
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ret = -EBUSY;
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DRM_ERROR("SVGA device lockup.\n");
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break;
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}
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schedule_timeout(1);
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if (interruptible && signal_pending(current)) {
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ret = -ERESTARTSYS;
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break;
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}
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}
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finish_wait(&dev_priv->fifo_queue, &__wait);
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wake_up_all(&dev_priv->fifo_queue);
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DRM_INFO("Fifo noirq exit.\n");
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return ret;
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}
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static int vmw_fifo_wait(struct vmw_private *dev_priv,
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uint32_t bytes, bool interruptible,
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unsigned long timeout)
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{
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long ret = 1L;
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if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
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return 0;
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vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
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if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
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return vmw_fifo_wait_noirq(dev_priv, bytes,
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interruptible, timeout);
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vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
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&dev_priv->fifo_queue_waiters);
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if (interruptible)
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ret = wait_event_interruptible_timeout
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(dev_priv->fifo_queue,
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!vmw_fifo_is_full(dev_priv, bytes), timeout);
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else
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ret = wait_event_timeout
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(dev_priv->fifo_queue,
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!vmw_fifo_is_full(dev_priv, bytes), timeout);
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if (unlikely(ret == 0))
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ret = -EBUSY;
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else if (likely(ret > 0))
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ret = 0;
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vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
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&dev_priv->fifo_queue_waiters);
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return ret;
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}
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/**
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* Reserve @bytes number of bytes in the fifo.
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*
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* This function will return NULL (error) on two conditions:
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* If it timeouts waiting for fifo space, or if @bytes is larger than the
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* available fifo space.
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*
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* Returns:
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* Pointer to the fifo, or null on error (possible hardware hang).
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*/
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static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
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uint32_t bytes)
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{
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struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t max;
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uint32_t min;
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uint32_t next_cmd;
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uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
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int ret;
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mutex_lock(&fifo_state->fifo_mutex);
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max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
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min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
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next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
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if (unlikely(bytes >= (max - min)))
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goto out_err;
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BUG_ON(fifo_state->reserved_size != 0);
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BUG_ON(fifo_state->dynamic_buffer != NULL);
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fifo_state->reserved_size = bytes;
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while (1) {
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uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP);
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bool need_bounce = false;
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bool reserve_in_place = false;
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if (next_cmd >= stop) {
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if (likely((next_cmd + bytes < max ||
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(next_cmd + bytes == max && stop > min))))
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reserve_in_place = true;
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else if (vmw_fifo_is_full(dev_priv, bytes)) {
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ret = vmw_fifo_wait(dev_priv, bytes,
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false, 3 * HZ);
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if (unlikely(ret != 0))
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goto out_err;
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} else
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need_bounce = true;
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} else {
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if (likely((next_cmd + bytes < stop)))
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reserve_in_place = true;
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else {
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ret = vmw_fifo_wait(dev_priv, bytes,
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false, 3 * HZ);
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if (unlikely(ret != 0))
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goto out_err;
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}
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}
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if (reserve_in_place) {
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if (reserveable || bytes <= sizeof(uint32_t)) {
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fifo_state->using_bounce_buffer = false;
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if (reserveable)
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vmw_mmio_write(bytes, fifo_mem +
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SVGA_FIFO_RESERVED);
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return (void __force *) (fifo_mem +
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(next_cmd >> 2));
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} else {
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need_bounce = true;
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}
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}
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if (need_bounce) {
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fifo_state->using_bounce_buffer = true;
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if (bytes < fifo_state->static_buffer_size)
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return fifo_state->static_buffer;
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else {
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fifo_state->dynamic_buffer = vmalloc(bytes);
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if (!fifo_state->dynamic_buffer)
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goto out_err;
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return fifo_state->dynamic_buffer;
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}
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}
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}
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out_err:
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fifo_state->reserved_size = 0;
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mutex_unlock(&fifo_state->fifo_mutex);
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return NULL;
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}
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void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes,
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int ctx_id)
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{
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void *ret;
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if (dev_priv->cman)
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ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
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ctx_id, false, NULL);
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else if (ctx_id == SVGA3D_INVALID_ID)
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ret = vmw_local_fifo_reserve(dev_priv, bytes);
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else {
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WARN(1, "Command buffer has not been allocated.\n");
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ret = NULL;
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}
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if (IS_ERR_OR_NULL(ret))
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return NULL;
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return ret;
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}
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static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
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u32 *fifo_mem,
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uint32_t next_cmd,
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uint32_t max, uint32_t min, uint32_t bytes)
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{
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uint32_t chunk_size = max - next_cmd;
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uint32_t rest;
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uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
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fifo_state->dynamic_buffer : fifo_state->static_buffer;
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if (bytes < chunk_size)
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chunk_size = bytes;
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vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED);
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mb();
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memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
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rest = bytes - chunk_size;
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if (rest)
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memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest);
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}
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static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
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u32 *fifo_mem,
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uint32_t next_cmd,
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uint32_t max, uint32_t min, uint32_t bytes)
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{
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uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
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fifo_state->dynamic_buffer : fifo_state->static_buffer;
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while (bytes > 0) {
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vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2));
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next_cmd += sizeof(uint32_t);
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if (unlikely(next_cmd == max))
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next_cmd = min;
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mb();
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vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
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mb();
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bytes -= sizeof(uint32_t);
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}
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}
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static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
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{
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struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
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u32 *fifo_mem = dev_priv->mmio_virt;
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uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD);
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uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX);
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uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN);
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bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
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if (fifo_state->dx)
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bytes += sizeof(struct vmw_temp_set_context);
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fifo_state->dx = false;
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BUG_ON((bytes & 3) != 0);
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BUG_ON(bytes > fifo_state->reserved_size);
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fifo_state->reserved_size = 0;
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if (fifo_state->using_bounce_buffer) {
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if (reserveable)
|
|
vmw_fifo_res_copy(fifo_state, fifo_mem,
|
|
next_cmd, max, min, bytes);
|
|
else
|
|
vmw_fifo_slow_copy(fifo_state, fifo_mem,
|
|
next_cmd, max, min, bytes);
|
|
|
|
if (fifo_state->dynamic_buffer) {
|
|
vfree(fifo_state->dynamic_buffer);
|
|
fifo_state->dynamic_buffer = NULL;
|
|
}
|
|
|
|
}
|
|
|
|
down_write(&fifo_state->rwsem);
|
|
if (fifo_state->using_bounce_buffer || reserveable) {
|
|
next_cmd += bytes;
|
|
if (next_cmd >= max)
|
|
next_cmd -= max - min;
|
|
mb();
|
|
vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
|
|
}
|
|
|
|
if (reserveable)
|
|
vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED);
|
|
mb();
|
|
up_write(&fifo_state->rwsem);
|
|
vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
|
|
mutex_unlock(&fifo_state->fifo_mutex);
|
|
}
|
|
|
|
void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
|
|
{
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
|
|
else
|
|
vmw_local_fifo_commit(dev_priv, bytes);
|
|
}
|
|
|
|
|
|
/**
|
|
* vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
|
|
*
|
|
* @dev_priv: Pointer to device private structure.
|
|
* @bytes: Number of bytes to commit.
|
|
*/
|
|
void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
|
|
{
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
|
|
else
|
|
vmw_local_fifo_commit(dev_priv, bytes);
|
|
}
|
|
|
|
/**
|
|
* vmw_fifo_flush - Flush any buffered commands and make sure command processing
|
|
* starts.
|
|
*
|
|
* @dev_priv: Pointer to device private structure.
|
|
* @interruptible: Whether to wait interruptible if function needs to sleep.
|
|
*/
|
|
int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
|
|
{
|
|
might_sleep();
|
|
|
|
if (dev_priv->cman)
|
|
return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
|
|
{
|
|
struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
|
|
struct svga_fifo_cmd_fence *cmd_fence;
|
|
u32 *fm;
|
|
int ret = 0;
|
|
uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
|
|
|
|
fm = VMW_FIFO_RESERVE(dev_priv, bytes);
|
|
if (unlikely(fm == NULL)) {
|
|
*seqno = atomic_read(&dev_priv->marker_seq);
|
|
ret = -ENOMEM;
|
|
(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
|
|
false, 3*HZ);
|
|
goto out_err;
|
|
}
|
|
|
|
do {
|
|
*seqno = atomic_add_return(1, &dev_priv->marker_seq);
|
|
} while (*seqno == 0);
|
|
|
|
if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
|
|
|
|
/*
|
|
* Don't request hardware to send a fence. The
|
|
* waiting code in vmwgfx_irq.c will emulate this.
|
|
*/
|
|
|
|
vmw_fifo_commit(dev_priv, 0);
|
|
return 0;
|
|
}
|
|
|
|
*fm++ = SVGA_CMD_FENCE;
|
|
cmd_fence = (struct svga_fifo_cmd_fence *) fm;
|
|
cmd_fence->fence = *seqno;
|
|
vmw_fifo_commit_flush(dev_priv, bytes);
|
|
(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
|
|
vmw_update_seqno(dev_priv, fifo_state);
|
|
|
|
out_err:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
|
|
* legacy query commands.
|
|
*
|
|
* @dev_priv: The device private structure.
|
|
* @cid: The hardware context id used for the query.
|
|
*
|
|
* See the vmw_fifo_emit_dummy_query documentation.
|
|
*/
|
|
static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
|
|
uint32_t cid)
|
|
{
|
|
/*
|
|
* A query wait without a preceding query end will
|
|
* actually finish all queries for this cid
|
|
* without writing to the query result structure.
|
|
*/
|
|
|
|
struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
|
|
struct {
|
|
SVGA3dCmdHeader header;
|
|
SVGA3dCmdWaitForQuery body;
|
|
} *cmd;
|
|
|
|
cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
|
|
if (unlikely(cmd == NULL))
|
|
return -ENOMEM;
|
|
|
|
cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
|
|
cmd->header.size = sizeof(cmd->body);
|
|
cmd->body.cid = cid;
|
|
cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
|
|
|
|
if (bo->mem.mem_type == TTM_PL_VRAM) {
|
|
cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
|
|
cmd->body.guestResult.offset = bo->mem.start << PAGE_SHIFT;
|
|
} else {
|
|
cmd->body.guestResult.gmrId = bo->mem.start;
|
|
cmd->body.guestResult.offset = 0;
|
|
}
|
|
|
|
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
|
|
* guest-backed resource query commands.
|
|
*
|
|
* @dev_priv: The device private structure.
|
|
* @cid: The hardware context id used for the query.
|
|
*
|
|
* See the vmw_fifo_emit_dummy_query documentation.
|
|
*/
|
|
static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
|
|
uint32_t cid)
|
|
{
|
|
/*
|
|
* A query wait without a preceding query end will
|
|
* actually finish all queries for this cid
|
|
* without writing to the query result structure.
|
|
*/
|
|
|
|
struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
|
|
struct {
|
|
SVGA3dCmdHeader header;
|
|
SVGA3dCmdWaitForGBQuery body;
|
|
} *cmd;
|
|
|
|
cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd));
|
|
if (unlikely(cmd == NULL))
|
|
return -ENOMEM;
|
|
|
|
cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
|
|
cmd->header.size = sizeof(cmd->body);
|
|
cmd->body.cid = cid;
|
|
cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
|
|
BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
|
|
cmd->body.mobid = bo->mem.start;
|
|
cmd->body.offset = 0;
|
|
|
|
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
|
|
* appropriate resource query commands.
|
|
*
|
|
* @dev_priv: The device private structure.
|
|
* @cid: The hardware context id used for the query.
|
|
*
|
|
* This function is used to emit a dummy occlusion query with
|
|
* no primitives rendered between query begin and query end.
|
|
* It's used to provide a query barrier, in order to know that when
|
|
* this query is finished, all preceding queries are also finished.
|
|
*
|
|
* A Query results structure should have been initialized at the start
|
|
* of the dev_priv->dummy_query_bo buffer object. And that buffer object
|
|
* must also be either reserved or pinned when this function is called.
|
|
*
|
|
* Returns -ENOMEM on failure to reserve fifo space.
|
|
*/
|
|
int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
|
|
uint32_t cid)
|
|
{
|
|
if (dev_priv->has_mob)
|
|
return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
|
|
|
|
return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
|
|
}
|