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907f53200f
The function always returns zero (success). Ideally we'll remove it all together - although that's requires a little more work. For now, we can drop the return type and simplify the drm core code surrounding it. v2: remove redundant assignment (Sam) Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Roland Scheidegger <sroland@vmware.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Cc: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Roland Scheidegger <sroland@vmware.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200530124640.4176323-1-emil.l.velikov@gmail.com
1535 lines
44 KiB
C
1535 lines
44 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/**************************************************************************
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*
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* Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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#include <linux/console.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/mem_encrypt.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_ioctl.h>
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#include <drm/drm_sysfs.h>
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#include <drm/ttm/ttm_bo_driver.h>
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#include <drm/ttm/ttm_module.h>
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#include <drm/ttm/ttm_placement.h>
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#include "ttm_object.h"
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#include "vmwgfx_binding.h"
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#include "vmwgfx_drv.h"
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#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
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#define VMWGFX_CHIP_SVGAII 0
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#define VMW_FB_RESERVATION 0
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#define VMW_MIN_INITIAL_WIDTH 800
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#define VMW_MIN_INITIAL_HEIGHT 600
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#ifndef VMWGFX_GIT_VERSION
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#define VMWGFX_GIT_VERSION "Unknown"
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#endif
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#define VMWGFX_REPO "In Tree"
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#define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
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/**
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* Fully encoded drm commands. Might move to vmw_drm.h
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*/
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#define DRM_IOCTL_VMW_GET_PARAM \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
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struct drm_vmw_getparam_arg)
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#define DRM_IOCTL_VMW_ALLOC_DMABUF \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
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union drm_vmw_alloc_dmabuf_arg)
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#define DRM_IOCTL_VMW_UNREF_DMABUF \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
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struct drm_vmw_unref_dmabuf_arg)
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#define DRM_IOCTL_VMW_CURSOR_BYPASS \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
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struct drm_vmw_cursor_bypass_arg)
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#define DRM_IOCTL_VMW_CONTROL_STREAM \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
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struct drm_vmw_control_stream_arg)
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#define DRM_IOCTL_VMW_CLAIM_STREAM \
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DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
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struct drm_vmw_stream_arg)
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#define DRM_IOCTL_VMW_UNREF_STREAM \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
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struct drm_vmw_stream_arg)
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#define DRM_IOCTL_VMW_CREATE_CONTEXT \
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DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
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struct drm_vmw_context_arg)
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#define DRM_IOCTL_VMW_UNREF_CONTEXT \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
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struct drm_vmw_context_arg)
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#define DRM_IOCTL_VMW_CREATE_SURFACE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
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union drm_vmw_surface_create_arg)
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#define DRM_IOCTL_VMW_UNREF_SURFACE \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
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struct drm_vmw_surface_arg)
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#define DRM_IOCTL_VMW_REF_SURFACE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
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union drm_vmw_surface_reference_arg)
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#define DRM_IOCTL_VMW_EXECBUF \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
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struct drm_vmw_execbuf_arg)
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#define DRM_IOCTL_VMW_GET_3D_CAP \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
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struct drm_vmw_get_3d_cap_arg)
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#define DRM_IOCTL_VMW_FENCE_WAIT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
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struct drm_vmw_fence_wait_arg)
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#define DRM_IOCTL_VMW_FENCE_SIGNALED \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
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struct drm_vmw_fence_signaled_arg)
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#define DRM_IOCTL_VMW_FENCE_UNREF \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
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struct drm_vmw_fence_arg)
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#define DRM_IOCTL_VMW_FENCE_EVENT \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
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struct drm_vmw_fence_event_arg)
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#define DRM_IOCTL_VMW_PRESENT \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
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struct drm_vmw_present_arg)
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#define DRM_IOCTL_VMW_PRESENT_READBACK \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
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struct drm_vmw_present_readback_arg)
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#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
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struct drm_vmw_update_layout_arg)
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#define DRM_IOCTL_VMW_CREATE_SHADER \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
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struct drm_vmw_shader_create_arg)
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#define DRM_IOCTL_VMW_UNREF_SHADER \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
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struct drm_vmw_shader_arg)
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#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
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union drm_vmw_gb_surface_create_arg)
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#define DRM_IOCTL_VMW_GB_SURFACE_REF \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
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union drm_vmw_gb_surface_reference_arg)
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#define DRM_IOCTL_VMW_SYNCCPU \
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DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
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struct drm_vmw_synccpu_arg)
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#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
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struct drm_vmw_context_arg)
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#define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \
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union drm_vmw_gb_surface_create_ext_arg)
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#define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \
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union drm_vmw_gb_surface_reference_ext_arg)
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#define DRM_IOCTL_VMW_MSG \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \
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struct drm_vmw_msg_arg)
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/**
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* The core DRM version of this macro doesn't account for
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* DRM_COMMAND_BASE.
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*/
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#define VMW_IOCTL_DEF(ioctl, func, flags) \
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[DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
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/**
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* Ioctl definitions.
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*/
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static const struct drm_ioctl_desc vmw_ioctls[] = {
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VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
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vmw_kms_cursor_bypass_ioctl,
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DRM_MASTER),
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VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
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DRM_MASTER),
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VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
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DRM_MASTER),
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VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
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DRM_MASTER),
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VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
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vmw_fence_obj_signaled_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
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DRM_RENDER_ALLOW),
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/* these allow direct access to the framebuffers mark as master only */
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VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
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DRM_MASTER | DRM_AUTH),
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VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
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vmw_present_readback_ioctl,
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DRM_MASTER | DRM_AUTH),
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/*
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* The permissions of the below ioctl are overridden in
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* vmw_generic_ioctl(). We require either
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* DRM_MASTER or capable(CAP_SYS_ADMIN).
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*/
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VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
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vmw_kms_update_layout_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_CREATE_SHADER,
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vmw_shader_define_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_UNREF_SHADER,
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vmw_shader_destroy_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
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vmw_gb_surface_define_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
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vmw_gb_surface_reference_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_SYNCCPU,
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vmw_user_bo_synccpu_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
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vmw_extended_context_define_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
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vmw_gb_surface_define_ext_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
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vmw_gb_surface_reference_ext_ioctl,
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DRM_RENDER_ALLOW),
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VMW_IOCTL_DEF(VMW_MSG,
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vmw_msg_ioctl,
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DRM_RENDER_ALLOW),
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};
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static const struct pci_device_id vmw_pci_id_list[] = {
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{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
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{0, 0, 0}
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};
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MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
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static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
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static int vmw_force_iommu;
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static int vmw_restrict_iommu;
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static int vmw_force_coherent;
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static int vmw_restrict_dma_mask;
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static int vmw_assume_16bpp;
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static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
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static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
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void *ptr);
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MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
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module_param_named(enable_fbdev, enable_fbdev, int, 0600);
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MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
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module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
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MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
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module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
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MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
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module_param_named(force_coherent, vmw_force_coherent, int, 0600);
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MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
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module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
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MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
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module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
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static void vmw_print_capabilities2(uint32_t capabilities2)
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{
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DRM_INFO("Capabilities2:\n");
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if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
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DRM_INFO(" Grow oTable.\n");
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if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
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DRM_INFO(" IntraSurface copy.\n");
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if (capabilities2 & SVGA_CAP2_DX3)
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DRM_INFO(" DX3.\n");
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}
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static void vmw_print_capabilities(uint32_t capabilities)
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{
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DRM_INFO("Capabilities:\n");
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if (capabilities & SVGA_CAP_RECT_COPY)
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DRM_INFO(" Rect copy.\n");
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if (capabilities & SVGA_CAP_CURSOR)
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DRM_INFO(" Cursor.\n");
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if (capabilities & SVGA_CAP_CURSOR_BYPASS)
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DRM_INFO(" Cursor bypass.\n");
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if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
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DRM_INFO(" Cursor bypass 2.\n");
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if (capabilities & SVGA_CAP_8BIT_EMULATION)
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DRM_INFO(" 8bit emulation.\n");
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if (capabilities & SVGA_CAP_ALPHA_CURSOR)
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DRM_INFO(" Alpha cursor.\n");
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if (capabilities & SVGA_CAP_3D)
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DRM_INFO(" 3D.\n");
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if (capabilities & SVGA_CAP_EXTENDED_FIFO)
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DRM_INFO(" Extended Fifo.\n");
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if (capabilities & SVGA_CAP_MULTIMON)
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DRM_INFO(" Multimon.\n");
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if (capabilities & SVGA_CAP_PITCHLOCK)
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DRM_INFO(" Pitchlock.\n");
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if (capabilities & SVGA_CAP_IRQMASK)
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DRM_INFO(" Irq mask.\n");
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if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
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DRM_INFO(" Display Topology.\n");
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if (capabilities & SVGA_CAP_GMR)
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DRM_INFO(" GMR.\n");
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if (capabilities & SVGA_CAP_TRACES)
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DRM_INFO(" Traces.\n");
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if (capabilities & SVGA_CAP_GMR2)
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DRM_INFO(" GMR2.\n");
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if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
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DRM_INFO(" Screen Object 2.\n");
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if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
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DRM_INFO(" Command Buffers.\n");
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if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
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DRM_INFO(" Command Buffers 2.\n");
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if (capabilities & SVGA_CAP_GBOBJECTS)
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DRM_INFO(" Guest Backed Resources.\n");
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if (capabilities & SVGA_CAP_DX)
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DRM_INFO(" DX Features.\n");
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if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
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DRM_INFO(" HP Command Queue.\n");
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}
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/**
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* vmw_dummy_query_bo_create - create a bo to hold a dummy query result
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*
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* @dev_priv: A device private structure.
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*
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* This function creates a small buffer object that holds the query
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* result for dummy queries emitted as query barriers.
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* The function will then map the first page and initialize a pending
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* occlusion query result structure, Finally it will unmap the buffer.
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* No interruptible waits are done within this function.
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*
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* Returns an error if bo creation or initialization fails.
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*/
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static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
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{
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int ret;
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struct vmw_buffer_object *vbo;
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struct ttm_bo_kmap_obj map;
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volatile SVGA3dQueryResult *result;
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bool dummy;
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/*
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* Create the vbo as pinned, so that a tryreserve will
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* immediately succeed. This is because we're the only
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* user of the bo currently.
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*/
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vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
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if (!vbo)
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return -ENOMEM;
|
|
|
|
ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
|
|
&vmw_sys_ne_placement, false,
|
|
&vmw_bo_bo_free);
|
|
if (unlikely(ret != 0))
|
|
return ret;
|
|
|
|
ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
|
|
BUG_ON(ret != 0);
|
|
vmw_bo_pin_reserved(vbo, true);
|
|
|
|
ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
|
|
if (likely(ret == 0)) {
|
|
result = ttm_kmap_obj_virtual(&map, &dummy);
|
|
result->totalSize = sizeof(*result);
|
|
result->state = SVGA3D_QUERYSTATE_PENDING;
|
|
result->result32 = 0xff;
|
|
ttm_bo_kunmap(&map);
|
|
}
|
|
vmw_bo_pin_reserved(vbo, false);
|
|
ttm_bo_unreserve(&vbo->base);
|
|
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Dummy query buffer map failed.\n");
|
|
vmw_bo_unreference(&vbo);
|
|
} else
|
|
dev_priv->dummy_query_bo = vbo;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* vmw_request_device_late - Perform late device setup
|
|
*
|
|
* @dev_priv: Pointer to device private.
|
|
*
|
|
* This function performs setup of otables and enables large command
|
|
* buffer submission. These tasks are split out to a separate function
|
|
* because it reverts vmw_release_device_early and is intended to be used
|
|
* by an error path in the hibernation code.
|
|
*/
|
|
static int vmw_request_device_late(struct vmw_private *dev_priv)
|
|
{
|
|
int ret;
|
|
|
|
if (dev_priv->has_mob) {
|
|
ret = vmw_otables_setup(dev_priv);
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Unable to initialize "
|
|
"guest Memory OBjects.\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (dev_priv->cman) {
|
|
ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
|
|
256*4096, 2*4096);
|
|
if (ret) {
|
|
struct vmw_cmdbuf_man *man = dev_priv->cman;
|
|
|
|
dev_priv->cman = NULL;
|
|
vmw_cmdbuf_man_destroy(man);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vmw_request_device(struct vmw_private *dev_priv)
|
|
{
|
|
int ret;
|
|
|
|
ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Unable to initialize FIFO.\n");
|
|
return ret;
|
|
}
|
|
vmw_fence_fifo_up(dev_priv->fman);
|
|
dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
|
|
if (IS_ERR(dev_priv->cman)) {
|
|
dev_priv->cman = NULL;
|
|
dev_priv->sm_type = VMW_SM_LEGACY;
|
|
}
|
|
|
|
ret = vmw_request_device_late(dev_priv);
|
|
if (ret)
|
|
goto out_no_mob;
|
|
|
|
ret = vmw_dummy_query_bo_create(dev_priv);
|
|
if (unlikely(ret != 0))
|
|
goto out_no_query_bo;
|
|
|
|
return 0;
|
|
|
|
out_no_query_bo:
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_remove_pool(dev_priv->cman);
|
|
if (dev_priv->has_mob) {
|
|
(void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
|
|
vmw_otables_takedown(dev_priv);
|
|
}
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_man_destroy(dev_priv->cman);
|
|
out_no_mob:
|
|
vmw_fence_fifo_down(dev_priv->fman);
|
|
vmw_fifo_release(dev_priv, &dev_priv->fifo);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* vmw_release_device_early - Early part of fifo takedown.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
*
|
|
* This is the first part of command submission takedown, to be called before
|
|
* buffer management is taken down.
|
|
*/
|
|
static void vmw_release_device_early(struct vmw_private *dev_priv)
|
|
{
|
|
/*
|
|
* Previous destructions should've released
|
|
* the pinned bo.
|
|
*/
|
|
|
|
BUG_ON(dev_priv->pinned_bo != NULL);
|
|
|
|
vmw_bo_unreference(&dev_priv->dummy_query_bo);
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_remove_pool(dev_priv->cman);
|
|
|
|
if (dev_priv->has_mob) {
|
|
ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
|
|
vmw_otables_takedown(dev_priv);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* vmw_release_device_late - Late part of fifo takedown.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
*
|
|
* This is the last part of the command submission takedown, to be called when
|
|
* command submission is no longer needed. It may wait on pending fences.
|
|
*/
|
|
static void vmw_release_device_late(struct vmw_private *dev_priv)
|
|
{
|
|
vmw_fence_fifo_down(dev_priv->fman);
|
|
if (dev_priv->cman)
|
|
vmw_cmdbuf_man_destroy(dev_priv->cman);
|
|
|
|
vmw_fifo_release(dev_priv, &dev_priv->fifo);
|
|
}
|
|
|
|
/**
|
|
* Sets the initial_[width|height] fields on the given vmw_private.
|
|
*
|
|
* It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
|
|
* clamping the value to fb_max_[width|height] fields and the
|
|
* VMW_MIN_INITIAL_[WIDTH|HEIGHT].
|
|
* If the values appear to be invalid, set them to
|
|
* VMW_MIN_INITIAL_[WIDTH|HEIGHT].
|
|
*/
|
|
static void vmw_get_initial_size(struct vmw_private *dev_priv)
|
|
{
|
|
uint32_t width;
|
|
uint32_t height;
|
|
|
|
width = vmw_read(dev_priv, SVGA_REG_WIDTH);
|
|
height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
|
|
|
|
width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
|
|
height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
|
|
|
|
if (width > dev_priv->fb_max_width ||
|
|
height > dev_priv->fb_max_height) {
|
|
|
|
/*
|
|
* This is a host error and shouldn't occur.
|
|
*/
|
|
|
|
width = VMW_MIN_INITIAL_WIDTH;
|
|
height = VMW_MIN_INITIAL_HEIGHT;
|
|
}
|
|
|
|
dev_priv->initial_width = width;
|
|
dev_priv->initial_height = height;
|
|
}
|
|
|
|
/**
|
|
* vmw_dma_select_mode - Determine how DMA mappings should be set up for this
|
|
* system.
|
|
*
|
|
* @dev_priv: Pointer to a struct vmw_private
|
|
*
|
|
* This functions tries to determine what actions need to be taken by the
|
|
* driver to make system pages visible to the device.
|
|
* If this function decides that DMA is not possible, it returns -EINVAL.
|
|
* The driver may then try to disable features of the device that require
|
|
* DMA.
|
|
*/
|
|
static int vmw_dma_select_mode(struct vmw_private *dev_priv)
|
|
{
|
|
static const char *names[vmw_dma_map_max] = {
|
|
[vmw_dma_phys] = "Using physical TTM page addresses.",
|
|
[vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
|
|
[vmw_dma_map_populate] = "Caching DMA mappings.",
|
|
[vmw_dma_map_bind] = "Giving up DMA mappings early."};
|
|
|
|
/* TTM currently doesn't fully support SEV encryption. */
|
|
if (mem_encrypt_active())
|
|
return -EINVAL;
|
|
|
|
if (vmw_force_coherent)
|
|
dev_priv->map_mode = vmw_dma_alloc_coherent;
|
|
else if (vmw_restrict_iommu)
|
|
dev_priv->map_mode = vmw_dma_map_bind;
|
|
else
|
|
dev_priv->map_mode = vmw_dma_map_populate;
|
|
|
|
if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) &&
|
|
(dev_priv->map_mode == vmw_dma_alloc_coherent))
|
|
return -EINVAL;
|
|
|
|
DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* vmw_dma_masks - set required page- and dma masks
|
|
*
|
|
* @dev: Pointer to struct drm-device
|
|
*
|
|
* With 32-bit we can only handle 32 bit PFNs. Optionally set that
|
|
* restriction also for 64-bit systems.
|
|
*/
|
|
static int vmw_dma_masks(struct vmw_private *dev_priv)
|
|
{
|
|
struct drm_device *dev = dev_priv->dev;
|
|
int ret = 0;
|
|
|
|
ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
|
|
if (dev_priv->map_mode != vmw_dma_phys &&
|
|
(sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
|
|
DRM_INFO("Restricting DMA addresses to 44 bits.\n");
|
|
return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
|
|
{
|
|
struct vmw_private *dev_priv;
|
|
int ret;
|
|
uint32_t svga_id;
|
|
enum vmw_res_type i;
|
|
bool refuse_dma = false;
|
|
char host_log[100] = {0};
|
|
|
|
dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
|
|
if (unlikely(!dev_priv)) {
|
|
DRM_ERROR("Failed allocating a device private struct.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pci_set_master(dev->pdev);
|
|
|
|
dev_priv->dev = dev;
|
|
dev_priv->vmw_chipset = chipset;
|
|
dev_priv->last_read_seqno = (uint32_t) -100;
|
|
mutex_init(&dev_priv->cmdbuf_mutex);
|
|
mutex_init(&dev_priv->release_mutex);
|
|
mutex_init(&dev_priv->binding_mutex);
|
|
mutex_init(&dev_priv->global_kms_state_mutex);
|
|
ttm_lock_init(&dev_priv->reservation_sem);
|
|
spin_lock_init(&dev_priv->resource_lock);
|
|
spin_lock_init(&dev_priv->hw_lock);
|
|
spin_lock_init(&dev_priv->waiter_lock);
|
|
spin_lock_init(&dev_priv->cap_lock);
|
|
spin_lock_init(&dev_priv->svga_lock);
|
|
spin_lock_init(&dev_priv->cursor_lock);
|
|
|
|
for (i = vmw_res_context; i < vmw_res_max; ++i) {
|
|
idr_init(&dev_priv->res_idr[i]);
|
|
INIT_LIST_HEAD(&dev_priv->res_lru[i]);
|
|
}
|
|
|
|
init_waitqueue_head(&dev_priv->fence_queue);
|
|
init_waitqueue_head(&dev_priv->fifo_queue);
|
|
dev_priv->fence_queue_waiters = 0;
|
|
dev_priv->fifo_queue_waiters = 0;
|
|
|
|
dev_priv->used_memory_size = 0;
|
|
|
|
dev_priv->io_start = pci_resource_start(dev->pdev, 0);
|
|
dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
|
|
dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
|
|
|
|
dev_priv->assume_16bpp = !!vmw_assume_16bpp;
|
|
|
|
dev_priv->enable_fb = enable_fbdev;
|
|
|
|
vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
|
|
svga_id = vmw_read(dev_priv, SVGA_REG_ID);
|
|
if (svga_id != SVGA_ID_2) {
|
|
ret = -ENOSYS;
|
|
DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
|
|
goto out_err0;
|
|
}
|
|
|
|
dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
|
|
|
|
if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
|
|
dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
|
|
}
|
|
|
|
|
|
ret = vmw_dma_select_mode(dev_priv);
|
|
if (unlikely(ret != 0)) {
|
|
DRM_INFO("Restricting capabilities since DMA not available.\n");
|
|
refuse_dma = true;
|
|
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
|
|
DRM_INFO("Disabling 3D acceleration.\n");
|
|
}
|
|
|
|
dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
|
|
dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
|
|
dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
|
|
dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
|
|
|
|
vmw_get_initial_size(dev_priv);
|
|
|
|
if (dev_priv->capabilities & SVGA_CAP_GMR2) {
|
|
dev_priv->max_gmr_ids =
|
|
vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
|
|
dev_priv->max_gmr_pages =
|
|
vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
|
|
dev_priv->memory_size =
|
|
vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
|
|
dev_priv->memory_size -= dev_priv->vram_size;
|
|
} else {
|
|
/*
|
|
* An arbitrary limit of 512MiB on surface
|
|
* memory. But all HWV8 hardware supports GMR2.
|
|
*/
|
|
dev_priv->memory_size = 512*1024*1024;
|
|
}
|
|
dev_priv->max_mob_pages = 0;
|
|
dev_priv->max_mob_size = 0;
|
|
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
|
|
uint64_t mem_size;
|
|
|
|
if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
|
|
mem_size = vmw_read(dev_priv,
|
|
SVGA_REG_GBOBJECT_MEM_SIZE_KB);
|
|
else
|
|
mem_size =
|
|
vmw_read(dev_priv,
|
|
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
|
|
|
|
/*
|
|
* Workaround for low memory 2D VMs to compensate for the
|
|
* allocation taken by fbdev
|
|
*/
|
|
if (!(dev_priv->capabilities & SVGA_CAP_3D))
|
|
mem_size *= 3;
|
|
|
|
dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
|
|
dev_priv->prim_bb_mem =
|
|
vmw_read(dev_priv,
|
|
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
|
|
dev_priv->max_mob_size =
|
|
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
|
|
dev_priv->stdu_max_width =
|
|
vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
|
|
dev_priv->stdu_max_height =
|
|
vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
|
|
|
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP,
|
|
SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
|
|
dev_priv->texture_max_width = vmw_read(dev_priv,
|
|
SVGA_REG_DEV_CAP);
|
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP,
|
|
SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
|
|
dev_priv->texture_max_height = vmw_read(dev_priv,
|
|
SVGA_REG_DEV_CAP);
|
|
} else {
|
|
dev_priv->texture_max_width = 8192;
|
|
dev_priv->texture_max_height = 8192;
|
|
dev_priv->prim_bb_mem = dev_priv->vram_size;
|
|
}
|
|
|
|
vmw_print_capabilities(dev_priv->capabilities);
|
|
if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
|
|
vmw_print_capabilities2(dev_priv->capabilities2);
|
|
|
|
ret = vmw_dma_masks(dev_priv);
|
|
if (unlikely(ret != 0))
|
|
goto out_err0;
|
|
|
|
dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK,
|
|
SCATTERLIST_MAX_SEGMENT));
|
|
|
|
if (dev_priv->capabilities & SVGA_CAP_GMR2) {
|
|
DRM_INFO("Max GMR ids is %u\n",
|
|
(unsigned)dev_priv->max_gmr_ids);
|
|
DRM_INFO("Max number of GMR pages is %u\n",
|
|
(unsigned)dev_priv->max_gmr_pages);
|
|
DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
|
|
(unsigned)dev_priv->memory_size / 1024);
|
|
}
|
|
DRM_INFO("Maximum display memory size is %u kiB\n",
|
|
dev_priv->prim_bb_mem / 1024);
|
|
DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
|
|
dev_priv->vram_start, dev_priv->vram_size / 1024);
|
|
DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
|
|
dev_priv->mmio_start, dev_priv->mmio_size / 1024);
|
|
|
|
dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
|
|
dev_priv->mmio_size, MEMREMAP_WB);
|
|
|
|
if (unlikely(dev_priv->mmio_virt == NULL)) {
|
|
ret = -ENOMEM;
|
|
DRM_ERROR("Failed mapping MMIO.\n");
|
|
goto out_err0;
|
|
}
|
|
|
|
/* Need mmio memory to check for fifo pitchlock cap. */
|
|
if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
|
|
!(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
|
|
!vmw_fifo_have_pitchlock(dev_priv)) {
|
|
ret = -ENOSYS;
|
|
DRM_ERROR("Hardware has no pitchlock\n");
|
|
goto out_err4;
|
|
}
|
|
|
|
dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
|
|
&vmw_prime_dmabuf_ops);
|
|
|
|
if (unlikely(dev_priv->tdev == NULL)) {
|
|
DRM_ERROR("Unable to initialize TTM object management.\n");
|
|
ret = -ENOMEM;
|
|
goto out_err4;
|
|
}
|
|
|
|
dev->dev_private = dev_priv;
|
|
|
|
ret = pci_request_regions(dev->pdev, "vmwgfx probe");
|
|
dev_priv->stealth = (ret != 0);
|
|
if (dev_priv->stealth) {
|
|
/**
|
|
* Request at least the mmio PCI resource.
|
|
*/
|
|
|
|
DRM_INFO("It appears like vesafb is loaded. "
|
|
"Ignore above error if any.\n");
|
|
ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
|
|
goto out_no_device;
|
|
}
|
|
}
|
|
|
|
if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
|
|
ret = vmw_irq_install(dev, dev->pdev->irq);
|
|
if (ret != 0) {
|
|
DRM_ERROR("Failed installing irq: %d\n", ret);
|
|
goto out_no_irq;
|
|
}
|
|
}
|
|
|
|
dev_priv->fman = vmw_fence_manager_init(dev_priv);
|
|
if (unlikely(dev_priv->fman == NULL)) {
|
|
ret = -ENOMEM;
|
|
goto out_no_fman;
|
|
}
|
|
|
|
drm_vma_offset_manager_init(&dev_priv->vma_manager,
|
|
DRM_FILE_PAGE_OFFSET_START,
|
|
DRM_FILE_PAGE_OFFSET_SIZE);
|
|
ret = ttm_bo_device_init(&dev_priv->bdev,
|
|
&vmw_bo_driver,
|
|
dev->anon_inode->i_mapping,
|
|
&dev_priv->vma_manager,
|
|
false);
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Failed initializing TTM buffer object driver.\n");
|
|
goto out_no_bdev;
|
|
}
|
|
|
|
/*
|
|
* Enable VRAM, but initially don't use it until SVGA is enabled and
|
|
* unhidden.
|
|
*/
|
|
ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
|
|
(dev_priv->vram_size >> PAGE_SHIFT));
|
|
if (unlikely(ret != 0)) {
|
|
DRM_ERROR("Failed initializing memory manager for VRAM.\n");
|
|
goto out_no_vram;
|
|
}
|
|
dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
|
|
|
|
dev_priv->has_gmr = true;
|
|
if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
|
|
refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
|
|
VMW_PL_GMR) != 0) {
|
|
DRM_INFO("No GMR memory available. "
|
|
"Graphics memory resources are very limited.\n");
|
|
dev_priv->has_gmr = false;
|
|
}
|
|
|
|
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
|
|
dev_priv->has_mob = true;
|
|
if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
|
|
VMW_PL_MOB) != 0) {
|
|
DRM_INFO("No MOB memory available. "
|
|
"3D will be disabled.\n");
|
|
dev_priv->has_mob = false;
|
|
}
|
|
}
|
|
|
|
if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
|
|
spin_lock(&dev_priv->cap_lock);
|
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
|
|
if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
|
|
dev_priv->sm_type = VMW_SM_4;
|
|
spin_unlock(&dev_priv->cap_lock);
|
|
}
|
|
|
|
vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
|
|
|
|
/* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
|
|
if (has_sm4_context(dev_priv) &&
|
|
(dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
|
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41);
|
|
|
|
if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
|
|
dev_priv->sm_type = VMW_SM_4_1;
|
|
|
|
if (has_sm4_1_context(dev_priv) &&
|
|
(dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
|
|
vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5);
|
|
if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
|
|
dev_priv->sm_type = VMW_SM_5;
|
|
}
|
|
}
|
|
|
|
ret = vmw_kms_init(dev_priv);
|
|
if (unlikely(ret != 0))
|
|
goto out_no_kms;
|
|
vmw_overlay_init(dev_priv);
|
|
|
|
ret = vmw_request_device(dev_priv);
|
|
if (ret)
|
|
goto out_no_fifo;
|
|
|
|
DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
|
|
? "yes." : "no.");
|
|
if (dev_priv->sm_type == VMW_SM_5)
|
|
DRM_INFO("SM5 support available.\n");
|
|
if (dev_priv->sm_type == VMW_SM_4_1)
|
|
DRM_INFO("SM4_1 support available.\n");
|
|
if (dev_priv->sm_type == VMW_SM_4)
|
|
DRM_INFO("SM4 support available.\n");
|
|
|
|
snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
|
|
VMWGFX_REPO, VMWGFX_GIT_VERSION);
|
|
vmw_host_log(host_log);
|
|
|
|
memset(host_log, 0, sizeof(host_log));
|
|
snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
|
|
VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
|
|
VMWGFX_DRIVER_PATCHLEVEL);
|
|
vmw_host_log(host_log);
|
|
|
|
if (dev_priv->enable_fb) {
|
|
vmw_fifo_resource_inc(dev_priv);
|
|
vmw_svga_enable(dev_priv);
|
|
vmw_fb_init(dev_priv);
|
|
}
|
|
|
|
dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
|
|
register_pm_notifier(&dev_priv->pm_nb);
|
|
|
|
return 0;
|
|
|
|
out_no_fifo:
|
|
vmw_overlay_close(dev_priv);
|
|
vmw_kms_close(dev_priv);
|
|
out_no_kms:
|
|
if (dev_priv->has_mob)
|
|
(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
|
|
if (dev_priv->has_gmr)
|
|
(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
|
|
(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
|
|
out_no_vram:
|
|
(void)ttm_bo_device_release(&dev_priv->bdev);
|
|
out_no_bdev:
|
|
vmw_fence_manager_takedown(dev_priv->fman);
|
|
out_no_fman:
|
|
if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
|
|
vmw_irq_uninstall(dev_priv->dev);
|
|
out_no_irq:
|
|
if (dev_priv->stealth)
|
|
pci_release_region(dev->pdev, 2);
|
|
else
|
|
pci_release_regions(dev->pdev);
|
|
out_no_device:
|
|
ttm_object_device_release(&dev_priv->tdev);
|
|
out_err4:
|
|
memunmap(dev_priv->mmio_virt);
|
|
out_err0:
|
|
for (i = vmw_res_context; i < vmw_res_max; ++i)
|
|
idr_destroy(&dev_priv->res_idr[i]);
|
|
|
|
if (dev_priv->ctx.staged_bindings)
|
|
vmw_binding_state_free(dev_priv->ctx.staged_bindings);
|
|
kfree(dev_priv);
|
|
return ret;
|
|
}
|
|
|
|
static void vmw_driver_unload(struct drm_device *dev)
|
|
{
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
enum vmw_res_type i;
|
|
|
|
unregister_pm_notifier(&dev_priv->pm_nb);
|
|
|
|
if (dev_priv->ctx.res_ht_initialized)
|
|
drm_ht_remove(&dev_priv->ctx.res_ht);
|
|
vfree(dev_priv->ctx.cmd_bounce);
|
|
if (dev_priv->enable_fb) {
|
|
vmw_fb_off(dev_priv);
|
|
vmw_fb_close(dev_priv);
|
|
vmw_fifo_resource_dec(dev_priv);
|
|
vmw_svga_disable(dev_priv);
|
|
}
|
|
|
|
vmw_kms_close(dev_priv);
|
|
vmw_overlay_close(dev_priv);
|
|
|
|
if (dev_priv->has_gmr)
|
|
(void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
|
|
(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
|
|
|
|
vmw_release_device_early(dev_priv);
|
|
if (dev_priv->has_mob)
|
|
(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
|
|
(void) ttm_bo_device_release(&dev_priv->bdev);
|
|
drm_vma_offset_manager_destroy(&dev_priv->vma_manager);
|
|
vmw_release_device_late(dev_priv);
|
|
vmw_fence_manager_takedown(dev_priv->fman);
|
|
if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
|
|
vmw_irq_uninstall(dev_priv->dev);
|
|
if (dev_priv->stealth)
|
|
pci_release_region(dev->pdev, 2);
|
|
else
|
|
pci_release_regions(dev->pdev);
|
|
|
|
ttm_object_device_release(&dev_priv->tdev);
|
|
memunmap(dev_priv->mmio_virt);
|
|
if (dev_priv->ctx.staged_bindings)
|
|
vmw_binding_state_free(dev_priv->ctx.staged_bindings);
|
|
|
|
for (i = vmw_res_context; i < vmw_res_max; ++i)
|
|
idr_destroy(&dev_priv->res_idr[i]);
|
|
|
|
kfree(dev_priv);
|
|
}
|
|
|
|
static void vmw_postclose(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
|
|
|
|
ttm_object_file_release(&vmw_fp->tfile);
|
|
kfree(vmw_fp);
|
|
}
|
|
|
|
static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
|
|
{
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
struct vmw_fpriv *vmw_fp;
|
|
int ret = -ENOMEM;
|
|
|
|
vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
|
|
if (unlikely(!vmw_fp))
|
|
return ret;
|
|
|
|
vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
|
|
if (unlikely(vmw_fp->tfile == NULL))
|
|
goto out_no_tfile;
|
|
|
|
file_priv->driver_priv = vmw_fp;
|
|
|
|
return 0;
|
|
|
|
out_no_tfile:
|
|
kfree(vmw_fp);
|
|
return ret;
|
|
}
|
|
|
|
static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg,
|
|
long (*ioctl_func)(struct file *, unsigned int,
|
|
unsigned long))
|
|
{
|
|
struct drm_file *file_priv = filp->private_data;
|
|
struct drm_device *dev = file_priv->minor->dev;
|
|
unsigned int nr = DRM_IOCTL_NR(cmd);
|
|
unsigned int flags;
|
|
|
|
/*
|
|
* Do extra checking on driver private ioctls.
|
|
*/
|
|
|
|
if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
|
|
&& (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
|
|
const struct drm_ioctl_desc *ioctl =
|
|
&vmw_ioctls[nr - DRM_COMMAND_BASE];
|
|
|
|
if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
|
|
return ioctl_func(filp, cmd, arg);
|
|
} else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
|
|
if (!drm_is_current_master(file_priv) &&
|
|
!capable(CAP_SYS_ADMIN))
|
|
return -EACCES;
|
|
}
|
|
|
|
if (unlikely(ioctl->cmd != cmd))
|
|
goto out_io_encoding;
|
|
|
|
flags = ioctl->flags;
|
|
} else if (!drm_ioctl_flags(nr, &flags))
|
|
return -EINVAL;
|
|
|
|
return ioctl_func(filp, cmd, arg);
|
|
|
|
out_io_encoding:
|
|
DRM_ERROR("Invalid command format, ioctl %d\n",
|
|
nr - DRM_COMMAND_BASE);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
|
|
}
|
|
#endif
|
|
|
|
static void vmw_master_set(struct drm_device *dev,
|
|
struct drm_file *file_priv,
|
|
bool from_open)
|
|
{
|
|
/*
|
|
* Inform a new master that the layout may have changed while
|
|
* it was gone.
|
|
*/
|
|
if (!from_open)
|
|
drm_sysfs_hotplug_event(dev);
|
|
}
|
|
|
|
static void vmw_master_drop(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
|
|
vmw_kms_legacy_hotspot_clear(dev_priv);
|
|
if (!dev_priv->enable_fb)
|
|
vmw_svga_disable(dev_priv);
|
|
}
|
|
|
|
/**
|
|
* __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
* Needs the reservation sem to be held in non-exclusive mode.
|
|
*/
|
|
static void __vmw_svga_enable(struct vmw_private *dev_priv)
|
|
{
|
|
spin_lock(&dev_priv->svga_lock);
|
|
if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
|
|
vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
|
|
dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
|
|
}
|
|
spin_unlock(&dev_priv->svga_lock);
|
|
}
|
|
|
|
/**
|
|
* vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
*/
|
|
void vmw_svga_enable(struct vmw_private *dev_priv)
|
|
{
|
|
(void) ttm_read_lock(&dev_priv->reservation_sem, false);
|
|
__vmw_svga_enable(dev_priv);
|
|
ttm_read_unlock(&dev_priv->reservation_sem);
|
|
}
|
|
|
|
/**
|
|
* __vmw_svga_disable - Disable SVGA mode and use of VRAM.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
* Needs the reservation sem to be held in exclusive mode.
|
|
* Will not empty VRAM. VRAM must be emptied by caller.
|
|
*/
|
|
static void __vmw_svga_disable(struct vmw_private *dev_priv)
|
|
{
|
|
spin_lock(&dev_priv->svga_lock);
|
|
if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
|
|
dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
|
|
vmw_write(dev_priv, SVGA_REG_ENABLE,
|
|
SVGA_REG_ENABLE_HIDE |
|
|
SVGA_REG_ENABLE_ENABLE);
|
|
}
|
|
spin_unlock(&dev_priv->svga_lock);
|
|
}
|
|
|
|
/**
|
|
* vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
|
|
* running.
|
|
*
|
|
* @dev_priv: Pointer to device private struct.
|
|
* Will empty VRAM.
|
|
*/
|
|
void vmw_svga_disable(struct vmw_private *dev_priv)
|
|
{
|
|
/*
|
|
* Disabling SVGA will turn off device modesetting capabilities, so
|
|
* notify KMS about that so that it doesn't cache atomic state that
|
|
* isn't valid anymore, for example crtcs turned on.
|
|
* Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
|
|
* but vmw_kms_lost_device() takes the reservation sem and thus we'll
|
|
* end up with lock order reversal. Thus, a master may actually perform
|
|
* a new modeset just after we call vmw_kms_lost_device() and race with
|
|
* vmw_svga_disable(), but that should at worst cause atomic KMS state
|
|
* to be inconsistent with the device, causing modesetting problems.
|
|
*
|
|
*/
|
|
vmw_kms_lost_device(dev_priv->dev);
|
|
ttm_write_lock(&dev_priv->reservation_sem, false);
|
|
spin_lock(&dev_priv->svga_lock);
|
|
if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
|
|
dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
|
|
spin_unlock(&dev_priv->svga_lock);
|
|
if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
|
|
DRM_ERROR("Failed evicting VRAM buffers.\n");
|
|
vmw_write(dev_priv, SVGA_REG_ENABLE,
|
|
SVGA_REG_ENABLE_HIDE |
|
|
SVGA_REG_ENABLE_ENABLE);
|
|
} else
|
|
spin_unlock(&dev_priv->svga_lock);
|
|
ttm_write_unlock(&dev_priv->reservation_sem);
|
|
}
|
|
|
|
static void vmw_remove(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
drm_dev_unregister(dev);
|
|
vmw_driver_unload(dev);
|
|
drm_dev_put(dev);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static unsigned long
|
|
vmw_get_unmapped_area(struct file *file, unsigned long uaddr,
|
|
unsigned long len, unsigned long pgoff,
|
|
unsigned long flags)
|
|
{
|
|
struct drm_file *file_priv = file->private_data;
|
|
struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev);
|
|
|
|
return drm_get_unmapped_area(file, uaddr, len, pgoff, flags,
|
|
&dev_priv->vma_manager);
|
|
}
|
|
|
|
static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
|
|
void *ptr)
|
|
{
|
|
struct vmw_private *dev_priv =
|
|
container_of(nb, struct vmw_private, pm_nb);
|
|
|
|
switch (val) {
|
|
case PM_HIBERNATION_PREPARE:
|
|
/*
|
|
* Take the reservation sem in write mode, which will make sure
|
|
* there are no other processes holding a buffer object
|
|
* reservation, meaning we should be able to evict all buffer
|
|
* objects if needed.
|
|
* Once user-space processes have been frozen, we can release
|
|
* the lock again.
|
|
*/
|
|
ttm_suspend_lock(&dev_priv->reservation_sem);
|
|
dev_priv->suspend_locked = true;
|
|
break;
|
|
case PM_POST_HIBERNATION:
|
|
case PM_POST_RESTORE:
|
|
if (READ_ONCE(dev_priv->suspend_locked)) {
|
|
dev_priv->suspend_locked = false;
|
|
ttm_suspend_unlock(&dev_priv->reservation_sem);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
|
|
if (dev_priv->refuse_hibernation)
|
|
return -EBUSY;
|
|
|
|
pci_save_state(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
|
return 0;
|
|
}
|
|
|
|
static int vmw_pci_resume(struct pci_dev *pdev)
|
|
{
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
return pci_enable_device(pdev);
|
|
}
|
|
|
|
static int vmw_pm_suspend(struct device *kdev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(kdev);
|
|
struct pm_message dummy;
|
|
|
|
dummy.event = 0;
|
|
|
|
return vmw_pci_suspend(pdev, dummy);
|
|
}
|
|
|
|
static int vmw_pm_resume(struct device *kdev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(kdev);
|
|
|
|
return vmw_pci_resume(pdev);
|
|
}
|
|
|
|
static int vmw_pm_freeze(struct device *kdev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(kdev);
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
int ret;
|
|
|
|
/*
|
|
* Unlock for vmw_kms_suspend.
|
|
* No user-space processes should be running now.
|
|
*/
|
|
ttm_suspend_unlock(&dev_priv->reservation_sem);
|
|
ret = vmw_kms_suspend(dev_priv->dev);
|
|
if (ret) {
|
|
ttm_suspend_lock(&dev_priv->reservation_sem);
|
|
DRM_ERROR("Failed to freeze modesetting.\n");
|
|
return ret;
|
|
}
|
|
if (dev_priv->enable_fb)
|
|
vmw_fb_off(dev_priv);
|
|
|
|
ttm_suspend_lock(&dev_priv->reservation_sem);
|
|
vmw_execbuf_release_pinned_bo(dev_priv);
|
|
vmw_resource_evict_all(dev_priv);
|
|
vmw_release_device_early(dev_priv);
|
|
ttm_bo_swapout_all(&dev_priv->bdev);
|
|
if (dev_priv->enable_fb)
|
|
vmw_fifo_resource_dec(dev_priv);
|
|
if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
|
|
DRM_ERROR("Can't hibernate while 3D resources are active.\n");
|
|
if (dev_priv->enable_fb)
|
|
vmw_fifo_resource_inc(dev_priv);
|
|
WARN_ON(vmw_request_device_late(dev_priv));
|
|
dev_priv->suspend_locked = false;
|
|
ttm_suspend_unlock(&dev_priv->reservation_sem);
|
|
if (dev_priv->suspend_state)
|
|
vmw_kms_resume(dev);
|
|
if (dev_priv->enable_fb)
|
|
vmw_fb_on(dev_priv);
|
|
return -EBUSY;
|
|
}
|
|
|
|
vmw_fence_fifo_down(dev_priv->fman);
|
|
__vmw_svga_disable(dev_priv);
|
|
|
|
vmw_release_device_late(dev_priv);
|
|
return 0;
|
|
}
|
|
|
|
static int vmw_pm_restore(struct device *kdev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(kdev);
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
struct vmw_private *dev_priv = vmw_priv(dev);
|
|
int ret;
|
|
|
|
vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
|
|
(void) vmw_read(dev_priv, SVGA_REG_ID);
|
|
|
|
if (dev_priv->enable_fb)
|
|
vmw_fifo_resource_inc(dev_priv);
|
|
|
|
ret = vmw_request_device(dev_priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (dev_priv->enable_fb)
|
|
__vmw_svga_enable(dev_priv);
|
|
|
|
vmw_fence_fifo_up(dev_priv->fman);
|
|
dev_priv->suspend_locked = false;
|
|
ttm_suspend_unlock(&dev_priv->reservation_sem);
|
|
if (dev_priv->suspend_state)
|
|
vmw_kms_resume(dev_priv->dev);
|
|
|
|
if (dev_priv->enable_fb)
|
|
vmw_fb_on(dev_priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops vmw_pm_ops = {
|
|
.freeze = vmw_pm_freeze,
|
|
.thaw = vmw_pm_restore,
|
|
.restore = vmw_pm_restore,
|
|
.suspend = vmw_pm_suspend,
|
|
.resume = vmw_pm_resume,
|
|
};
|
|
|
|
static const struct file_operations vmwgfx_driver_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = vmw_unlocked_ioctl,
|
|
.mmap = vmw_mmap,
|
|
.poll = vmw_fops_poll,
|
|
.read = vmw_fops_read,
|
|
#if defined(CONFIG_COMPAT)
|
|
.compat_ioctl = vmw_compat_ioctl,
|
|
#endif
|
|
.llseek = noop_llseek,
|
|
.get_unmapped_area = vmw_get_unmapped_area,
|
|
};
|
|
|
|
static struct drm_driver driver = {
|
|
.driver_features =
|
|
DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC,
|
|
.ioctls = vmw_ioctls,
|
|
.num_ioctls = ARRAY_SIZE(vmw_ioctls),
|
|
.master_set = vmw_master_set,
|
|
.master_drop = vmw_master_drop,
|
|
.open = vmw_driver_open,
|
|
.postclose = vmw_postclose,
|
|
|
|
.dumb_create = vmw_dumb_create,
|
|
.dumb_map_offset = vmw_dumb_map_offset,
|
|
.dumb_destroy = vmw_dumb_destroy,
|
|
|
|
.prime_fd_to_handle = vmw_prime_fd_to_handle,
|
|
.prime_handle_to_fd = vmw_prime_handle_to_fd,
|
|
|
|
.fops = &vmwgfx_driver_fops,
|
|
.name = VMWGFX_DRIVER_NAME,
|
|
.desc = VMWGFX_DRIVER_DESC,
|
|
.date = VMWGFX_DRIVER_DATE,
|
|
.major = VMWGFX_DRIVER_MAJOR,
|
|
.minor = VMWGFX_DRIVER_MINOR,
|
|
.patchlevel = VMWGFX_DRIVER_PATCHLEVEL
|
|
};
|
|
|
|
static struct pci_driver vmw_pci_driver = {
|
|
.name = VMWGFX_DRIVER_NAME,
|
|
.id_table = vmw_pci_id_list,
|
|
.probe = vmw_probe,
|
|
.remove = vmw_remove,
|
|
.driver = {
|
|
.pm = &vmw_pm_ops
|
|
}
|
|
};
|
|
|
|
static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct drm_device *dev;
|
|
int ret;
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev = drm_dev_alloc(&driver, &pdev->dev);
|
|
if (IS_ERR(dev)) {
|
|
ret = PTR_ERR(dev);
|
|
goto err_pci_disable_device;
|
|
}
|
|
|
|
dev->pdev = pdev;
|
|
pci_set_drvdata(pdev, dev);
|
|
|
|
ret = vmw_driver_load(dev, ent->driver_data);
|
|
if (ret)
|
|
goto err_drm_dev_put;
|
|
|
|
ret = drm_dev_register(dev, ent->driver_data);
|
|
if (ret)
|
|
goto err_vmw_driver_unload;
|
|
|
|
return 0;
|
|
|
|
err_vmw_driver_unload:
|
|
vmw_driver_unload(dev);
|
|
err_drm_dev_put:
|
|
drm_dev_put(dev);
|
|
err_pci_disable_device:
|
|
pci_disable_device(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static int __init vmwgfx_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (vgacon_text_force())
|
|
return -EINVAL;
|
|
|
|
ret = pci_register_driver(&vmw_pci_driver);
|
|
if (ret)
|
|
DRM_ERROR("Failed initializing DRM.\n");
|
|
return ret;
|
|
}
|
|
|
|
static void __exit vmwgfx_exit(void)
|
|
{
|
|
pci_unregister_driver(&vmw_pci_driver);
|
|
}
|
|
|
|
module_init(vmwgfx_init);
|
|
module_exit(vmwgfx_exit);
|
|
|
|
MODULE_AUTHOR("VMware Inc. and others");
|
|
MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
|
|
MODULE_LICENSE("GPL and additional rights");
|
|
MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
|
|
__stringify(VMWGFX_DRIVER_MINOR) "."
|
|
__stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
|
|
"0");
|