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2b86189e4d
Spelling out _unlocked for each and every driver is a annoying. Especially if we consider how many drivers, do not know (or need to) about the horror stories involving struct_mutex. Just drop the suffix. It makes the API cleaner. Done via the following script: __from=drm_gem_object_put_unlocked __to=drm_gem_object_put for __file in $(git grep --name-only $__from); do sed -i "s/$__from/$__to/g" $__file; done Cc: Eric Anholt <eric@anholt.net> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200515095118.2743122-33-emil.l.velikov@gmail.com
293 lines
7.2 KiB
C
293 lines
7.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2014-2018 Broadcom */
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/**
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* DOC: Interrupt management for the V3D engine
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*
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* When we take a bin, render, TFU done, or CSD done interrupt, we
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* need to signal the fence for that job so that the scheduler can
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* queue up the next one and unblock any waiters.
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*
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* When we take the binner out of memory interrupt, we need to
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* allocate some new memory and pass it to the binner so that the
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* current job can make progress.
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*/
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#include <linux/platform_device.h>
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#include "v3d_drv.h"
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#include "v3d_regs.h"
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#include "v3d_trace.h"
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#define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
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V3D_INT_FLDONE | \
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V3D_INT_FRDONE | \
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V3D_INT_CSDDONE | \
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V3D_INT_GMPV))
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#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
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V3D_HUB_INT_MMU_PTI | \
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V3D_HUB_INT_MMU_CAP | \
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V3D_HUB_INT_TFUC))
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static irqreturn_t
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v3d_hub_irq(int irq, void *arg);
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static void
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v3d_overflow_mem_work(struct work_struct *work)
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{
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struct v3d_dev *v3d =
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container_of(work, struct v3d_dev, overflow_mem_work);
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struct drm_device *dev = &v3d->drm;
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struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
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struct drm_gem_object *obj;
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unsigned long irqflags;
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if (IS_ERR(bo)) {
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DRM_ERROR("Couldn't allocate binner overflow mem\n");
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return;
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}
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obj = &bo->base.base;
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/* We lost a race, and our work task came in after the bin job
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* completed and exited. This can happen because the HW
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* signals OOM before it's fully OOM, so the binner might just
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* barely complete.
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*
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* If we lose the race and our work task comes in after a new
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* bin job got scheduled, that's fine. We'll just give them
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* some binner pool anyway.
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*/
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spin_lock_irqsave(&v3d->job_lock, irqflags);
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if (!v3d->bin_job) {
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spin_unlock_irqrestore(&v3d->job_lock, irqflags);
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goto out;
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}
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drm_gem_object_get(obj);
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list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
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spin_unlock_irqrestore(&v3d->job_lock, irqflags);
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V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
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V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
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out:
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drm_gem_object_put(obj);
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}
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static irqreturn_t
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v3d_irq(int irq, void *arg)
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{
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struct v3d_dev *v3d = arg;
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u32 intsts;
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irqreturn_t status = IRQ_NONE;
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intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
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/* Acknowledge the interrupts we're handling here. */
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V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
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if (intsts & V3D_INT_OUTOMEM) {
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/* Note that the OOM status is edge signaled, so the
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* interrupt won't happen again until the we actually
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* add more memory. Also, as of V3D 4.1, FLDONE won't
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* be reported until any OOM state has been cleared.
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*/
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schedule_work(&v3d->overflow_mem_work);
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status = IRQ_HANDLED;
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}
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if (intsts & V3D_INT_FLDONE) {
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struct v3d_fence *fence =
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to_v3d_fence(v3d->bin_job->base.irq_fence);
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trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
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dma_fence_signal(&fence->base);
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status = IRQ_HANDLED;
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}
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if (intsts & V3D_INT_FRDONE) {
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struct v3d_fence *fence =
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to_v3d_fence(v3d->render_job->base.irq_fence);
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trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
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dma_fence_signal(&fence->base);
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status = IRQ_HANDLED;
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}
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if (intsts & V3D_INT_CSDDONE) {
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struct v3d_fence *fence =
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to_v3d_fence(v3d->csd_job->base.irq_fence);
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trace_v3d_csd_irq(&v3d->drm, fence->seqno);
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dma_fence_signal(&fence->base);
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status = IRQ_HANDLED;
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}
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/* We shouldn't be triggering these if we have GMP in
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* always-allowed mode.
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*/
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if (intsts & V3D_INT_GMPV)
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dev_err(v3d->drm.dev, "GMP violation\n");
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/* V3D 4.2 wires the hub and core IRQs together, so if we &
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* didn't see the common one then check hub for MMU IRQs.
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*/
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if (v3d->single_irq_line && status == IRQ_NONE)
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return v3d_hub_irq(irq, arg);
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return status;
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}
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static irqreturn_t
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v3d_hub_irq(int irq, void *arg)
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{
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struct v3d_dev *v3d = arg;
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u32 intsts;
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irqreturn_t status = IRQ_NONE;
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intsts = V3D_READ(V3D_HUB_INT_STS);
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/* Acknowledge the interrupts we're handling here. */
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V3D_WRITE(V3D_HUB_INT_CLR, intsts);
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if (intsts & V3D_HUB_INT_TFUC) {
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struct v3d_fence *fence =
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to_v3d_fence(v3d->tfu_job->base.irq_fence);
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trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
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dma_fence_signal(&fence->base);
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status = IRQ_HANDLED;
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}
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if (intsts & (V3D_HUB_INT_MMU_WRV |
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V3D_HUB_INT_MMU_PTI |
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V3D_HUB_INT_MMU_CAP)) {
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u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
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u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
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(v3d->va_width - 32));
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static const char *const v3d41_axi_ids[] = {
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"L2T",
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"PTB",
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"PSE",
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"TLB",
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"CLE",
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"TFU",
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"MMU",
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"GMP",
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};
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const char *client = "?";
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V3D_WRITE(V3D_MMU_CTL,
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V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
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V3D_MMU_CTL_PT_INVALID |
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V3D_MMU_CTL_WRITE_VIOLATION));
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if (v3d->ver >= 41) {
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axi_id = axi_id >> 5;
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if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
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client = v3d41_axi_ids[axi_id];
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}
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dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
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client, axi_id, (long long)vio_addr,
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((intsts & V3D_HUB_INT_MMU_WRV) ?
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", write violation" : ""),
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((intsts & V3D_HUB_INT_MMU_PTI) ?
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", pte invalid" : ""),
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((intsts & V3D_HUB_INT_MMU_CAP) ?
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", cap exceeded" : ""));
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status = IRQ_HANDLED;
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}
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return status;
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}
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int
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v3d_irq_init(struct v3d_dev *v3d)
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{
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int irq1, ret, core;
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INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
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/* Clear any pending interrupts someone might have left around
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* for us.
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*/
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for (core = 0; core < v3d->cores; core++)
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V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
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V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
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irq1 = platform_get_irq(v3d_to_pdev(v3d), 1);
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if (irq1 == -EPROBE_DEFER)
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return irq1;
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if (irq1 > 0) {
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ret = devm_request_irq(v3d->drm.dev, irq1,
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v3d_irq, IRQF_SHARED,
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"v3d_core0", v3d);
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if (ret)
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goto fail;
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ret = devm_request_irq(v3d->drm.dev,
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platform_get_irq(v3d_to_pdev(v3d), 0),
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v3d_hub_irq, IRQF_SHARED,
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"v3d_hub", v3d);
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if (ret)
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goto fail;
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} else {
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v3d->single_irq_line = true;
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ret = devm_request_irq(v3d->drm.dev,
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platform_get_irq(v3d_to_pdev(v3d), 0),
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v3d_irq, IRQF_SHARED,
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"v3d", v3d);
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if (ret)
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goto fail;
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}
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v3d_irq_enable(v3d);
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return 0;
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fail:
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if (ret != -EPROBE_DEFER)
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dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
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return ret;
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}
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void
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v3d_irq_enable(struct v3d_dev *v3d)
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{
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int core;
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/* Enable our set of interrupts, masking out any others. */
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for (core = 0; core < v3d->cores; core++) {
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V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
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V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
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}
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V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
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V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
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}
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void
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v3d_irq_disable(struct v3d_dev *v3d)
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{
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int core;
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/* Disable all interrupts. */
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for (core = 0; core < v3d->cores; core++)
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V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
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V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
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/* Clear any pending interrupts we might have left. */
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for (core = 0; core < v3d->cores; core++)
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V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
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V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
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cancel_work_sync(&v3d->overflow_mem_work);
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}
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/** Reinitializes interrupt registers when a GPU reset is performed. */
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void v3d_irq_reset(struct v3d_dev *v3d)
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{
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v3d_irq_enable(v3d);
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}
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