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0dc9b286b8
Store ttm bo->offset in struct nouveau_bo instead. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.freedesktop.org/patch/372932/ Signed-off-by: Christian König <christian.koenig@amd.com>
1716 lines
43 KiB
C
1716 lines
43 KiB
C
/*
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* Copyright 2007 Dave Airlied
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Authors: Dave Airlied <airlied@linux.ie>
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* Ben Skeggs <darktama@iinet.net.au>
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* Jeremy Kolb <jkolb@brandeis.edu>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/swiotlb.h>
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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#include "nouveau_bo.h"
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#include "nouveau_ttm.h"
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#include "nouveau_gem.h"
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#include "nouveau_mem.h"
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#include "nouveau_vmm.h"
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#include <nvif/class.h>
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#include <nvif/if500b.h>
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#include <nvif/if900b.h>
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/*
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* NV10-NV40 tiling helpers
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*/
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static void
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nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
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u32 addr, u32 size, u32 pitch, u32 flags)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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int i = reg - drm->tile.reg;
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struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
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struct nvkm_fb_tile *tile = &fb->tile.region[i];
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nouveau_fence_unref(®->fence);
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if (tile->pitch)
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nvkm_fb_tile_fini(fb, i, tile);
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if (pitch)
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nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
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nvkm_fb_tile_prog(fb, i, tile);
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}
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static struct nouveau_drm_tile *
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nv10_bo_get_tile_region(struct drm_device *dev, int i)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_drm_tile *tile = &drm->tile.reg[i];
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spin_lock(&drm->tile.lock);
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if (!tile->used &&
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(!tile->fence || nouveau_fence_done(tile->fence)))
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tile->used = true;
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else
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tile = NULL;
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spin_unlock(&drm->tile.lock);
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return tile;
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}
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static void
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nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
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struct dma_fence *fence)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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if (tile) {
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spin_lock(&drm->tile.lock);
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tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
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tile->used = false;
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spin_unlock(&drm->tile.lock);
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}
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}
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static struct nouveau_drm_tile *
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nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
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u32 size, u32 pitch, u32 zeta)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
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struct nouveau_drm_tile *tile, *found = NULL;
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int i;
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for (i = 0; i < fb->tile.regions; i++) {
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tile = nv10_bo_get_tile_region(dev, i);
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if (pitch && !found) {
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found = tile;
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continue;
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} else if (tile && fb->tile.region[i].pitch) {
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/* Kill an unused tile region. */
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nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
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}
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nv10_bo_put_tile_region(dev, tile, NULL);
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}
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if (found)
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nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
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return found;
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}
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static void
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nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
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{
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struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
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struct drm_device *dev = drm->dev;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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WARN_ON(nvbo->pin_refcnt > 0);
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nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
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/*
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* If nouveau_bo_new() allocated this buffer, the GEM object was never
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* initialized, so don't attempt to release it.
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*/
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if (bo->base.dev)
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drm_gem_object_release(&bo->base);
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kfree(nvbo);
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}
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static inline u64
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roundup_64(u64 x, u32 y)
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{
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x += y - 1;
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do_div(x, y);
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return x * y;
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}
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static void
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nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
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int *align, u64 *size)
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{
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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struct nvif_device *device = &drm->client.device;
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if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
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if (nvbo->mode) {
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if (device->info.chipset >= 0x40) {
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*align = 65536;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x30) {
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*align = 32768;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x20) {
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*align = 16384;
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*size = roundup_64(*size, 64 * nvbo->mode);
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} else if (device->info.chipset >= 0x10) {
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*align = 16384;
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*size = roundup_64(*size, 32 * nvbo->mode);
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}
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}
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} else {
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*size = roundup_64(*size, (1 << nvbo->page));
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*align = max((1 << nvbo->page), *align);
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}
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*size = roundup_64(*size, PAGE_SIZE);
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}
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struct nouveau_bo *
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nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags,
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u32 tile_mode, u32 tile_flags)
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{
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struct nouveau_drm *drm = cli->drm;
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struct nouveau_bo *nvbo;
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struct nvif_mmu *mmu = &cli->mmu;
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struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
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int i, pi = -1;
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if (!*size) {
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NV_WARN(drm, "skipped size %016llx\n", *size);
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return ERR_PTR(-EINVAL);
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}
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nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
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if (!nvbo)
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return ERR_PTR(-ENOMEM);
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INIT_LIST_HEAD(&nvbo->head);
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INIT_LIST_HEAD(&nvbo->entry);
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INIT_LIST_HEAD(&nvbo->vma_list);
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nvbo->bo.bdev = &drm->ttm.bdev;
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/* This is confusing, and doesn't actually mean we want an uncached
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* mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
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* into in nouveau_gem_new().
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*/
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if (flags & TTM_PL_FLAG_UNCACHED) {
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/* Determine if we can get a cache-coherent map, forcing
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* uncached mapping if we can't.
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*/
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if (!nouveau_drm_use_coherent_gpu_mapping(drm))
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nvbo->force_coherent = true;
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}
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
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nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
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if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
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kfree(nvbo);
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return ERR_PTR(-EINVAL);
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}
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nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
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} else
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if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
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nvbo->kind = (tile_flags & 0x00007f00) >> 8;
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nvbo->comp = (tile_flags & 0x00030000) >> 16;
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if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
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kfree(nvbo);
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return ERR_PTR(-EINVAL);
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}
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} else {
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nvbo->zeta = (tile_flags & 0x00000007);
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}
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nvbo->mode = tile_mode;
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nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
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/* Determine the desirable target GPU page size for the buffer. */
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for (i = 0; i < vmm->page_nr; i++) {
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/* Because we cannot currently allow VMM maps to fail
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* during buffer migration, we need to determine page
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* size for the buffer up-front, and pre-allocate its
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* page tables.
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*
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* Skip page sizes that can't support needed domains.
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*/
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if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
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(flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram)
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continue;
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if ((flags & TTM_PL_FLAG_TT) &&
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(!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
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continue;
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/* Select this page size if it's the first that supports
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* the potential memory domains, or when it's compatible
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* with the requested compression settings.
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*/
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if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
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pi = i;
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/* Stop once the buffer is larger than the current page size. */
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if (*size >= 1ULL << vmm->page[i].shift)
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break;
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}
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if (WARN_ON(pi < 0))
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return ERR_PTR(-EINVAL);
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/* Disable compression if suitable settings couldn't be found. */
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if (nvbo->comp && !vmm->page[pi].comp) {
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if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
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nvbo->kind = mmu->kind[nvbo->kind];
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nvbo->comp = 0;
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}
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nvbo->page = vmm->page[pi].shift;
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nouveau_bo_fixup_align(nvbo, flags, align, size);
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return nvbo;
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}
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int
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nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags,
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struct sg_table *sg, struct dma_resv *robj)
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{
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int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
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size_t acc_size;
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int ret;
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acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo));
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nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
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nouveau_bo_placement_set(nvbo, flags, 0);
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ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type,
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&nvbo->placement, align >> PAGE_SHIFT, false,
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acc_size, sg, robj, nouveau_bo_del_ttm);
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if (ret) {
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/* ttm will call nouveau_bo_del_ttm if it fails.. */
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return ret;
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}
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return 0;
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}
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int
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nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
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uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
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struct sg_table *sg, struct dma_resv *robj,
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struct nouveau_bo **pnvbo)
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{
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struct nouveau_bo *nvbo;
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int ret;
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nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode,
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tile_flags);
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if (IS_ERR(nvbo))
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return PTR_ERR(nvbo);
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ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj);
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if (ret)
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return ret;
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*pnvbo = nvbo;
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return 0;
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}
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static void
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set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
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{
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*n = 0;
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if (type & TTM_PL_FLAG_VRAM)
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pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
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if (type & TTM_PL_FLAG_TT)
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pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
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if (type & TTM_PL_FLAG_SYSTEM)
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pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
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}
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static void
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set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
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{
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT;
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unsigned i, fpfn, lpfn;
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if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
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nvbo->mode && (type & TTM_PL_FLAG_VRAM) &&
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nvbo->bo.mem.num_pages < vram_pages / 4) {
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/*
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* Make sure that the color and depth buffers are handled
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* by independent memory controller units. Up to a 9x
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* speed up when alpha-blending and depth-test are enabled
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* at the same time.
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*/
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if (nvbo->zeta) {
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fpfn = vram_pages / 2;
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lpfn = ~0;
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} else {
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fpfn = 0;
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lpfn = vram_pages / 2;
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}
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for (i = 0; i < nvbo->placement.num_placement; ++i) {
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nvbo->placements[i].fpfn = fpfn;
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nvbo->placements[i].lpfn = lpfn;
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}
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for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
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nvbo->busy_placements[i].fpfn = fpfn;
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nvbo->busy_placements[i].lpfn = lpfn;
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}
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}
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}
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void
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nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
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{
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struct ttm_placement *pl = &nvbo->placement;
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uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
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TTM_PL_MASK_CACHING) |
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(nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
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pl->placement = nvbo->placements;
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set_placement_list(nvbo->placements, &pl->num_placement,
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type, flags);
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pl->busy_placement = nvbo->busy_placements;
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set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
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type | busy, flags);
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set_placement_range(nvbo, type);
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}
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|
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int
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nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
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{
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
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struct ttm_buffer_object *bo = &nvbo->bo;
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bool force = false, evict = false;
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int ret;
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ret = ttm_bo_reserve(bo, false, false, NULL);
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if (ret)
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return ret;
|
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|
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if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
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memtype == TTM_PL_FLAG_VRAM && contig) {
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if (!nvbo->contig) {
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nvbo->contig = true;
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force = true;
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evict = true;
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}
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}
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|
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if (nvbo->pin_refcnt) {
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if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
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NV_ERROR(drm, "bo %p pinned elsewhere: "
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"0x%08x vs 0x%08x\n", bo,
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1 << bo->mem.mem_type, memtype);
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ret = -EBUSY;
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}
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nvbo->pin_refcnt++;
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goto out;
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}
|
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|
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if (evict) {
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nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
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ret = nouveau_bo_validate(nvbo, false, false);
|
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if (ret)
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goto out;
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}
|
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|
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nvbo->pin_refcnt++;
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nouveau_bo_placement_set(nvbo, memtype, 0);
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|
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/* drop pin_refcnt temporarily, so we don't trip the assertion
|
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* in nouveau_bo_move() that makes sure we're not trying to
|
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* move a pinned buffer
|
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*/
|
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nvbo->pin_refcnt--;
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ret = nouveau_bo_validate(nvbo, false, false);
|
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if (ret)
|
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goto out;
|
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nvbo->pin_refcnt++;
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|
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switch (bo->mem.mem_type) {
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case TTM_PL_VRAM:
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drm->gem.vram_available -= bo->mem.size;
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break;
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case TTM_PL_TT:
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drm->gem.gart_available -= bo->mem.size;
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break;
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default:
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break;
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}
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out:
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if (force && ret)
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nvbo->contig = false;
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ttm_bo_unreserve(bo);
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return ret;
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}
|
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|
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int
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nouveau_bo_unpin(struct nouveau_bo *nvbo)
|
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{
|
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struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
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struct ttm_buffer_object *bo = &nvbo->bo;
|
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int ret, ref;
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|
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ret = ttm_bo_reserve(bo, false, false, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ref = --nvbo->pin_refcnt;
|
|
WARN_ON_ONCE(ref < 0);
|
|
if (ref)
|
|
goto out;
|
|
|
|
nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
|
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
if (ret == 0) {
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
drm->gem.vram_available += bo->mem.size;
|
|
break;
|
|
case TTM_PL_TT:
|
|
drm->gem.gart_available += bo->mem.size;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
out:
|
|
ttm_bo_unreserve(bo);
|
|
return ret;
|
|
}
|
|
|
|
int
|
|
nouveau_bo_map(struct nouveau_bo *nvbo)
|
|
{
|
|
int ret;
|
|
|
|
ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
|
|
|
|
ttm_bo_unreserve(&nvbo->bo);
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_unmap(struct nouveau_bo *nvbo)
|
|
{
|
|
if (!nvbo)
|
|
return;
|
|
|
|
ttm_bo_kunmap(&nvbo->kmap);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
|
|
int i;
|
|
|
|
if (!ttm_dma)
|
|
return;
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
if (nvbo->force_coherent)
|
|
return;
|
|
|
|
for (i = 0; i < ttm_dma->ttm.num_pages; i++)
|
|
dma_sync_single_for_device(drm->dev->dev,
|
|
ttm_dma->dma_address[i],
|
|
PAGE_SIZE, DMA_TO_DEVICE);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
|
|
struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
|
|
int i;
|
|
|
|
if (!ttm_dma)
|
|
return;
|
|
|
|
/* Don't waste time looping if the object is coherent */
|
|
if (nvbo->force_coherent)
|
|
return;
|
|
|
|
for (i = 0; i < ttm_dma->ttm.num_pages; i++)
|
|
dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
}
|
|
|
|
int
|
|
nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
|
|
bool no_wait_gpu)
|
|
{
|
|
struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
|
|
int ret;
|
|
|
|
ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nouveau_bo_sync_for_device(nvbo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
|
|
{
|
|
bool is_iomem;
|
|
u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
iowrite16_native(val, (void __force __iomem *)mem);
|
|
else
|
|
*mem = val;
|
|
}
|
|
|
|
u32
|
|
nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
|
|
{
|
|
bool is_iomem;
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
return ioread32_native((void __force __iomem *)mem);
|
|
else
|
|
return *mem;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
|
|
{
|
|
bool is_iomem;
|
|
u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
|
|
|
|
mem += index;
|
|
|
|
if (is_iomem)
|
|
iowrite32_native(val, (void __force __iomem *)mem);
|
|
else
|
|
*mem = val;
|
|
}
|
|
|
|
static struct ttm_tt *
|
|
nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
|
|
{
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
|
|
if (drm->agp.bridge) {
|
|
return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
|
|
}
|
|
#endif
|
|
|
|
return nouveau_sgdma_create_ttm(bo, page_flags);
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
|
|
struct ttm_mem_type_manager *man)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
struct nvif_mmu *mmu = &drm->client.mmu;
|
|
|
|
switch (type) {
|
|
case TTM_PL_SYSTEM:
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
|
|
man->available_caching = TTM_PL_MASK_CACHING;
|
|
man->default_caching = TTM_PL_FLAG_CACHED;
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
man->flags = TTM_MEMTYPE_FLAG_FIXED |
|
|
TTM_MEMTYPE_FLAG_MAPPABLE;
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED |
|
|
TTM_PL_FLAG_WC;
|
|
man->default_caching = TTM_PL_FLAG_WC;
|
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
|
/* Some BARs do not support being ioremapped WC */
|
|
const u8 type = mmu->type[drm->ttm.type_vram].type;
|
|
if (type & NVIF_MEM_UNCACHED) {
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED;
|
|
man->default_caching = TTM_PL_FLAG_UNCACHED;
|
|
}
|
|
|
|
man->func = &nouveau_vram_manager;
|
|
man->io_reserve_fastpath = false;
|
|
man->use_io_reserve_lru = true;
|
|
} else {
|
|
man->func = &ttm_bo_manager_func;
|
|
}
|
|
break;
|
|
case TTM_PL_TT:
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA)
|
|
man->func = &nouveau_gart_manager;
|
|
else
|
|
if (!drm->agp.bridge)
|
|
man->func = &nv04_gart_manager;
|
|
else
|
|
man->func = &ttm_bo_manager_func;
|
|
|
|
if (drm->agp.bridge) {
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
|
|
man->available_caching = TTM_PL_FLAG_UNCACHED |
|
|
TTM_PL_FLAG_WC;
|
|
man->default_caching = TTM_PL_FLAG_WC;
|
|
} else {
|
|
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
|
|
TTM_MEMTYPE_FLAG_CMA;
|
|
man->available_caching = TTM_PL_MASK_CACHING;
|
|
man->default_caching = TTM_PL_FLAG_CACHED;
|
|
}
|
|
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
|
|
{
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
switch (bo->mem.mem_type) {
|
|
case TTM_PL_VRAM:
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
|
|
TTM_PL_FLAG_SYSTEM);
|
|
break;
|
|
default:
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
|
|
break;
|
|
}
|
|
|
|
*pl = nvbo->placement;
|
|
}
|
|
|
|
|
|
static int
|
|
nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
{
|
|
int ret = RING_SPACE(chan, 2);
|
|
if (ret == 0) {
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
|
|
OUT_RING (chan, handle & 0x0000ffff);
|
|
FIRE_RING (chan);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
int ret = RING_SPACE(chan, 10);
|
|
if (ret == 0) {
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, new_reg->num_pages);
|
|
BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
{
|
|
int ret = RING_SPACE(chan, 2);
|
|
if (ret == 0) {
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
|
|
OUT_RING (chan, handle);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
u64 src_offset = mem->vma[0].addr;
|
|
u64 dst_offset = mem->vma[1].addr;
|
|
u32 page_count = new_reg->num_pages;
|
|
int ret;
|
|
|
|
page_count = new_reg->num_pages;
|
|
while (page_count) {
|
|
int line_count = (page_count > 8191) ? 8191 : page_count;
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, line_count);
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
|
|
OUT_RING (chan, 0x00000110);
|
|
|
|
page_count -= line_count;
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
u64 src_offset = mem->vma[0].addr;
|
|
u64 dst_offset = mem->vma[1].addr;
|
|
u32 page_count = new_reg->num_pages;
|
|
int ret;
|
|
|
|
page_count = new_reg->num_pages;
|
|
while (page_count) {
|
|
int line_count = (page_count > 2047) ? 2047 : page_count;
|
|
|
|
ret = RING_SPACE(chan, 12);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
OUT_RING (chan, PAGE_SIZE); /* src_pitch */
|
|
OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
|
|
OUT_RING (chan, PAGE_SIZE); /* line_length */
|
|
OUT_RING (chan, line_count);
|
|
BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
|
|
OUT_RING (chan, 0x00100110);
|
|
|
|
page_count -= line_count;
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
u64 src_offset = mem->vma[0].addr;
|
|
u64 dst_offset = mem->vma[1].addr;
|
|
u32 page_count = new_reg->num_pages;
|
|
int ret;
|
|
|
|
page_count = new_reg->num_pages;
|
|
while (page_count) {
|
|
int line_count = (page_count > 8191) ? 8191 : page_count;
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, PAGE_SIZE);
|
|
OUT_RING (chan, line_count);
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
|
|
OUT_RING (chan, 0x00000110);
|
|
|
|
page_count -= line_count;
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
int ret = RING_SPACE(chan, 7);
|
|
if (ret == 0) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, 0x00000000 /* COPY */);
|
|
OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
int ret = RING_SPACE(chan, 7);
|
|
if (ret == 0) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
|
|
OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT);
|
|
OUT_RING (chan, upper_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[0].addr));
|
|
OUT_RING (chan, upper_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, lower_32_bits(mem->vma[1].addr));
|
|
OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
{
|
|
int ret = RING_SPACE(chan, 6);
|
|
if (ret == 0) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
|
|
OUT_RING (chan, handle);
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
|
|
OUT_RING (chan, chan->drm->ntfy.handle);
|
|
OUT_RING (chan, chan->vram.handle);
|
|
OUT_RING (chan, chan->vram.handle);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = nouveau_mem(old_reg);
|
|
u64 length = (new_reg->num_pages << PAGE_SHIFT);
|
|
u64 src_offset = mem->vma[0].addr;
|
|
u64 dst_offset = mem->vma[1].addr;
|
|
int src_tiled = !!mem->kind;
|
|
int dst_tiled = !!nouveau_mem(new_reg)->kind;
|
|
int ret;
|
|
|
|
while (length) {
|
|
u32 amount, stride, height;
|
|
|
|
ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
|
|
if (ret)
|
|
return ret;
|
|
|
|
amount = min(length, (u64)(4 * 1024 * 1024));
|
|
stride = 16 * 4;
|
|
height = amount / stride;
|
|
|
|
if (src_tiled) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, stride);
|
|
OUT_RING (chan, height);
|
|
OUT_RING (chan, 1);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, 0);
|
|
} else {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
|
|
OUT_RING (chan, 1);
|
|
}
|
|
if (dst_tiled) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, stride);
|
|
OUT_RING (chan, height);
|
|
OUT_RING (chan, 1);
|
|
OUT_RING (chan, 0);
|
|
OUT_RING (chan, 0);
|
|
} else {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
|
|
OUT_RING (chan, 1);
|
|
}
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
|
|
OUT_RING (chan, upper_32_bits(src_offset));
|
|
OUT_RING (chan, upper_32_bits(dst_offset));
|
|
BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
|
|
OUT_RING (chan, lower_32_bits(src_offset));
|
|
OUT_RING (chan, lower_32_bits(dst_offset));
|
|
OUT_RING (chan, stride);
|
|
OUT_RING (chan, stride);
|
|
OUT_RING (chan, stride);
|
|
OUT_RING (chan, height);
|
|
OUT_RING (chan, 0x00000101);
|
|
OUT_RING (chan, 0x00000000);
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
|
|
OUT_RING (chan, 0);
|
|
|
|
length -= amount;
|
|
src_offset += amount;
|
|
dst_offset += amount;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
|
|
{
|
|
int ret = RING_SPACE(chan, 4);
|
|
if (ret == 0) {
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
|
|
OUT_RING (chan, handle);
|
|
BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
|
|
OUT_RING (chan, chan->drm->ntfy.handle);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static inline uint32_t
|
|
nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
|
|
struct nouveau_channel *chan, struct ttm_mem_reg *reg)
|
|
{
|
|
if (reg->mem_type == TTM_PL_TT)
|
|
return NvDmaTT;
|
|
return chan->vram.handle;
|
|
}
|
|
|
|
static int
|
|
nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
|
|
{
|
|
u32 src_offset = old_reg->start << PAGE_SHIFT;
|
|
u32 dst_offset = new_reg->start << PAGE_SHIFT;
|
|
u32 page_count = new_reg->num_pages;
|
|
int ret;
|
|
|
|
ret = RING_SPACE(chan, 3);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
|
|
OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg));
|
|
OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg));
|
|
|
|
page_count = new_reg->num_pages;
|
|
while (page_count) {
|
|
int line_count = (page_count > 2047) ? 2047 : page_count;
|
|
|
|
ret = RING_SPACE(chan, 11);
|
|
if (ret)
|
|
return ret;
|
|
|
|
BEGIN_NV04(chan, NvSubCopy,
|
|
NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
|
|
OUT_RING (chan, src_offset);
|
|
OUT_RING (chan, dst_offset);
|
|
OUT_RING (chan, PAGE_SIZE); /* src_pitch */
|
|
OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
|
|
OUT_RING (chan, PAGE_SIZE); /* line_length */
|
|
OUT_RING (chan, line_count);
|
|
OUT_RING (chan, 0x00000101);
|
|
OUT_RING (chan, 0x00000000);
|
|
BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
|
|
OUT_RING (chan, 0);
|
|
|
|
page_count -= line_count;
|
|
src_offset += (PAGE_SIZE * line_count);
|
|
dst_offset += (PAGE_SIZE * line_count);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *reg)
|
|
{
|
|
struct nouveau_mem *old_mem = nouveau_mem(&bo->mem);
|
|
struct nouveau_mem *new_mem = nouveau_mem(reg);
|
|
struct nvif_vmm *vmm = &drm->client.vmm.vmm;
|
|
int ret;
|
|
|
|
ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
|
|
old_mem->mem.size, &old_mem->vma[0]);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
|
|
new_mem->mem.size, &old_mem->vma[1]);
|
|
if (ret)
|
|
goto done;
|
|
|
|
ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
|
|
if (ret)
|
|
goto done;
|
|
|
|
ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
|
|
done:
|
|
if (ret) {
|
|
nvif_vmm_put(vmm, &old_mem->vma[1]);
|
|
nvif_vmm_put(vmm, &old_mem->vma[0]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_channel *chan = drm->ttm.chan;
|
|
struct nouveau_cli *cli = (void *)chan->user.client;
|
|
struct nouveau_fence *fence;
|
|
int ret;
|
|
|
|
/* create temporary vmas for the transfer and attach them to the
|
|
* old nvkm_mem node, these will get cleaned up after ttm has
|
|
* destroyed the ttm_mem_reg
|
|
*/
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
|
|
ret = nouveau_bo_move_prep(drm, bo, new_reg);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
|
|
ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
|
|
if (ret == 0) {
|
|
ret = drm->ttm.move(chan, bo, &bo->mem, new_reg);
|
|
if (ret == 0) {
|
|
ret = nouveau_fence_new(chan, false, &fence);
|
|
if (ret == 0) {
|
|
ret = ttm_bo_move_accel_cleanup(bo,
|
|
&fence->base,
|
|
evict,
|
|
new_reg);
|
|
nouveau_fence_unref(&fence);
|
|
}
|
|
}
|
|
}
|
|
mutex_unlock(&cli->mutex);
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
nouveau_bo_move_init(struct nouveau_drm *drm)
|
|
{
|
|
static const struct _method_table {
|
|
const char *name;
|
|
int engine;
|
|
s32 oclass;
|
|
int (*exec)(struct nouveau_channel *,
|
|
struct ttm_buffer_object *,
|
|
struct ttm_mem_reg *, struct ttm_mem_reg *);
|
|
int (*init)(struct nouveau_channel *, u32 handle);
|
|
} _methods[] = {
|
|
{ "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
|
|
{ "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
|
|
{ "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
|
|
{ "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
|
|
{ "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
|
|
{ "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
|
|
{ "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
|
|
{},
|
|
{ "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
|
|
};
|
|
const struct _method_table *mthd = _methods;
|
|
const char *name = "CPU";
|
|
int ret;
|
|
|
|
do {
|
|
struct nouveau_channel *chan;
|
|
|
|
if (mthd->engine)
|
|
chan = drm->cechan;
|
|
else
|
|
chan = drm->channel;
|
|
if (chan == NULL)
|
|
continue;
|
|
|
|
ret = nvif_object_init(&chan->user,
|
|
mthd->oclass | (mthd->engine << 16),
|
|
mthd->oclass, NULL, 0,
|
|
&drm->ttm.copy);
|
|
if (ret == 0) {
|
|
ret = mthd->init(chan, drm->ttm.copy.handle);
|
|
if (ret) {
|
|
nvif_object_fini(&drm->ttm.copy);
|
|
continue;
|
|
}
|
|
|
|
drm->ttm.move = mthd->exec;
|
|
drm->ttm.chan = chan;
|
|
name = mthd->name;
|
|
break;
|
|
}
|
|
} while ((++mthd)->exec);
|
|
|
|
NV_INFO(drm, "MM: using %s for buffer copies\n", name);
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
|
|
struct ttm_place placement_memtype = {
|
|
.fpfn = 0,
|
|
.lpfn = 0,
|
|
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
|
|
};
|
|
struct ttm_placement placement;
|
|
struct ttm_mem_reg tmp_reg;
|
|
int ret;
|
|
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
|
|
|
tmp_reg = *new_reg;
|
|
tmp_reg.mm_node = NULL;
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = ttm_bo_move_ttm(bo, &ctx, new_reg);
|
|
out:
|
|
ttm_bo_mem_put(bo, &tmp_reg);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
|
|
bool no_wait_gpu, struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct ttm_operation_ctx ctx = { intr, no_wait_gpu };
|
|
struct ttm_place placement_memtype = {
|
|
.fpfn = 0,
|
|
.lpfn = 0,
|
|
.flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
|
|
};
|
|
struct ttm_placement placement;
|
|
struct ttm_mem_reg tmp_reg;
|
|
int ret;
|
|
|
|
placement.num_placement = placement.num_busy_placement = 1;
|
|
placement.placement = placement.busy_placement = &placement_memtype;
|
|
|
|
tmp_reg = *new_reg;
|
|
tmp_reg.mm_node = NULL;
|
|
ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg);
|
|
if (ret)
|
|
goto out;
|
|
|
|
out:
|
|
ttm_bo_mem_put(bo, &tmp_reg);
|
|
return ret;
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct nouveau_vma *vma;
|
|
|
|
/* ttm can now (stupidly) pass the driver bos it didn't create... */
|
|
if (bo->destroy != nouveau_bo_del_ttm)
|
|
return;
|
|
|
|
if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
|
|
mem->mem.page == nvbo->page) {
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
|
nouveau_vma_map(vma, mem);
|
|
}
|
|
} else {
|
|
list_for_each_entry(vma, &nvbo->vma_list, head) {
|
|
WARN_ON(ttm_bo_wait(bo, false, false));
|
|
nouveau_vma_unmap(vma);
|
|
}
|
|
}
|
|
|
|
if (new_reg) {
|
|
if (new_reg->mm_node)
|
|
nvbo->offset = (new_reg->start << PAGE_SHIFT);
|
|
else
|
|
nvbo->offset = 0;
|
|
}
|
|
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg,
|
|
struct nouveau_drm_tile **new_tile)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = drm->dev;
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
u64 offset = new_reg->start << PAGE_SHIFT;
|
|
|
|
*new_tile = NULL;
|
|
if (new_reg->mem_type != TTM_PL_VRAM)
|
|
return 0;
|
|
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
|
|
*new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size,
|
|
nvbo->mode, nvbo->zeta);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
|
|
struct nouveau_drm_tile *new_tile,
|
|
struct nouveau_drm_tile **old_tile)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct drm_device *dev = drm->dev;
|
|
struct dma_fence *fence = dma_resv_get_excl(bo->base.resv);
|
|
|
|
nv10_bo_put_tile_region(dev, *old_tile, fence);
|
|
*old_tile = new_tile;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
|
|
struct ttm_operation_ctx *ctx,
|
|
struct ttm_mem_reg *new_reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct ttm_mem_reg *old_reg = &bo->mem;
|
|
struct nouveau_drm_tile *new_tile = NULL;
|
|
int ret = 0;
|
|
|
|
ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (nvbo->pin_refcnt)
|
|
NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
|
|
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
|
ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* Fake bo copy. */
|
|
if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
|
|
BUG_ON(bo->mem.mm_node != NULL);
|
|
bo->mem = *new_reg;
|
|
new_reg->mm_node = NULL;
|
|
goto out;
|
|
}
|
|
|
|
/* Hardware assisted copy. */
|
|
if (drm->ttm.move) {
|
|
if (new_reg->mem_type == TTM_PL_SYSTEM)
|
|
ret = nouveau_bo_move_flipd(bo, evict,
|
|
ctx->interruptible,
|
|
ctx->no_wait_gpu, new_reg);
|
|
else if (old_reg->mem_type == TTM_PL_SYSTEM)
|
|
ret = nouveau_bo_move_flips(bo, evict,
|
|
ctx->interruptible,
|
|
ctx->no_wait_gpu, new_reg);
|
|
else
|
|
ret = nouveau_bo_move_m2mf(bo, evict,
|
|
ctx->interruptible,
|
|
ctx->no_wait_gpu, new_reg);
|
|
if (!ret)
|
|
goto out;
|
|
}
|
|
|
|
/* Fallback to software copy. */
|
|
ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
|
|
if (ret == 0)
|
|
ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
|
|
|
|
out:
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
|
|
if (ret)
|
|
nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
|
|
else
|
|
nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|
{
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
|
|
return drm_vma_node_verify_access(&nvbo->bo.base.vma_node,
|
|
filp->private_data);
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
|
{
|
|
struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type];
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
|
|
|
reg->bus.addr = NULL;
|
|
reg->bus.offset = 0;
|
|
reg->bus.size = reg->num_pages << PAGE_SHIFT;
|
|
reg->bus.base = 0;
|
|
reg->bus.is_iomem = false;
|
|
if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
|
|
return -EINVAL;
|
|
switch (reg->mem_type) {
|
|
case TTM_PL_SYSTEM:
|
|
/* System memory */
|
|
return 0;
|
|
case TTM_PL_TT:
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
if (drm->agp.bridge) {
|
|
reg->bus.offset = reg->start << PAGE_SHIFT;
|
|
reg->bus.base = drm->agp.base;
|
|
reg->bus.is_iomem = !drm->agp.cma;
|
|
}
|
|
#endif
|
|
if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
|
|
/* untiled */
|
|
break;
|
|
/* fall through - tiled memory */
|
|
case TTM_PL_VRAM:
|
|
reg->bus.offset = reg->start << PAGE_SHIFT;
|
|
reg->bus.base = device->func->resource_addr(device, 1);
|
|
reg->bus.is_iomem = true;
|
|
if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
|
|
union {
|
|
struct nv50_mem_map_v0 nv50;
|
|
struct gf100_mem_map_v0 gf100;
|
|
} args;
|
|
u64 handle, length;
|
|
u32 argc = 0;
|
|
int ret;
|
|
|
|
switch (mem->mem.object.oclass) {
|
|
case NVIF_CLASS_MEM_NV50:
|
|
args.nv50.version = 0;
|
|
args.nv50.ro = 0;
|
|
args.nv50.kind = mem->kind;
|
|
args.nv50.comp = mem->comp;
|
|
argc = sizeof(args.nv50);
|
|
break;
|
|
case NVIF_CLASS_MEM_GF100:
|
|
args.gf100.version = 0;
|
|
args.gf100.ro = 0;
|
|
args.gf100.kind = mem->kind;
|
|
argc = sizeof(args.gf100);
|
|
break;
|
|
default:
|
|
WARN_ON(1);
|
|
break;
|
|
}
|
|
|
|
ret = nvif_object_map_handle(&mem->mem.object,
|
|
&args, argc,
|
|
&handle, &length);
|
|
if (ret != 1) {
|
|
if (WARN_ON(ret == 0))
|
|
return -EINVAL;
|
|
if (ret == -ENOSPC)
|
|
return -EAGAIN;
|
|
return ret;
|
|
}
|
|
|
|
reg->bus.base = 0;
|
|
reg->bus.offset = handle;
|
|
}
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bdev);
|
|
struct nouveau_mem *mem = nouveau_mem(reg);
|
|
|
|
if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
|
|
switch (reg->mem_type) {
|
|
case TTM_PL_TT:
|
|
if (mem->kind)
|
|
nvif_object_unmap_handle(&mem->mem.object);
|
|
break;
|
|
case TTM_PL_VRAM:
|
|
nvif_object_unmap_handle(&mem->mem.object);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
|
|
struct nouveau_bo *nvbo = nouveau_bo(bo);
|
|
struct nvkm_device *device = nvxx_device(&drm->client.device);
|
|
u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
|
|
int i, ret;
|
|
|
|
/* as long as the bo isn't in vram, and isn't tiled, we've got
|
|
* nothing to do here.
|
|
*/
|
|
if (bo->mem.mem_type != TTM_PL_VRAM) {
|
|
if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
|
|
!nvbo->kind)
|
|
return 0;
|
|
|
|
if (bo->mem.mem_type == TTM_PL_SYSTEM) {
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
|
|
|
|
ret = nouveau_bo_validate(nvbo, false, false);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* make sure bo is in mappable vram */
|
|
if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
|
|
bo->mem.start + bo->mem.num_pages < mappable)
|
|
return 0;
|
|
|
|
for (i = 0; i < nvbo->placement.num_placement; ++i) {
|
|
nvbo->placements[i].fpfn = 0;
|
|
nvbo->placements[i].lpfn = mappable;
|
|
}
|
|
|
|
for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
|
|
nvbo->busy_placements[i].fpfn = 0;
|
|
nvbo->busy_placements[i].lpfn = mappable;
|
|
}
|
|
|
|
nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
|
|
return nouveau_bo_validate(nvbo, false, false);
|
|
}
|
|
|
|
static int
|
|
nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
|
|
{
|
|
struct ttm_dma_tt *ttm_dma = (void *)ttm;
|
|
struct nouveau_drm *drm;
|
|
struct device *dev;
|
|
unsigned i;
|
|
int r;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (ttm->state != tt_unpopulated)
|
|
return 0;
|
|
|
|
if (slave && ttm->sg) {
|
|
/* make userspace faulting work */
|
|
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
|
ttm_dma->dma_address, ttm->num_pages);
|
|
ttm->state = tt_unbound;
|
|
return 0;
|
|
}
|
|
|
|
drm = nouveau_bdev(ttm->bdev);
|
|
dev = drm->dev->dev;
|
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
if (drm->agp.bridge) {
|
|
return ttm_agp_tt_populate(ttm, ctx);
|
|
}
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
|
|
if (swiotlb_nr_tbl()) {
|
|
return ttm_dma_populate((void *)ttm, dev, ctx);
|
|
}
|
|
#endif
|
|
|
|
r = ttm_pool_populate(ttm, ctx);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
|
dma_addr_t addr;
|
|
|
|
addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE,
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dev, addr)) {
|
|
while (i--) {
|
|
dma_unmap_page(dev, ttm_dma->dma_address[i],
|
|
PAGE_SIZE, DMA_BIDIRECTIONAL);
|
|
ttm_dma->dma_address[i] = 0;
|
|
}
|
|
ttm_pool_unpopulate(ttm);
|
|
return -EFAULT;
|
|
}
|
|
|
|
ttm_dma->dma_address[i] = addr;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
|
{
|
|
struct ttm_dma_tt *ttm_dma = (void *)ttm;
|
|
struct nouveau_drm *drm;
|
|
struct device *dev;
|
|
unsigned i;
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
if (slave)
|
|
return;
|
|
|
|
drm = nouveau_bdev(ttm->bdev);
|
|
dev = drm->dev->dev;
|
|
|
|
#if IS_ENABLED(CONFIG_AGP)
|
|
if (drm->agp.bridge) {
|
|
ttm_agp_tt_unpopulate(ttm);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
|
|
if (swiotlb_nr_tbl()) {
|
|
ttm_dma_unpopulate((void *)ttm, dev);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
|
if (ttm_dma->dma_address[i]) {
|
|
dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE,
|
|
DMA_BIDIRECTIONAL);
|
|
}
|
|
}
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
}
|
|
|
|
void
|
|
nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
|
|
{
|
|
struct dma_resv *resv = nvbo->bo.base.resv;
|
|
|
|
if (exclusive)
|
|
dma_resv_add_excl_fence(resv, &fence->base);
|
|
else if (fence)
|
|
dma_resv_add_shared_fence(resv, &fence->base);
|
|
}
|
|
|
|
struct ttm_bo_driver nouveau_bo_driver = {
|
|
.ttm_tt_create = &nouveau_ttm_tt_create,
|
|
.ttm_tt_populate = &nouveau_ttm_tt_populate,
|
|
.ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
|
|
.init_mem_type = nouveau_bo_init_mem_type,
|
|
.eviction_valuable = ttm_bo_eviction_valuable,
|
|
.evict_flags = nouveau_bo_evict_flags,
|
|
.move_notify = nouveau_bo_move_ntfy,
|
|
.move = nouveau_bo_move,
|
|
.verify_access = nouveau_bo_verify_access,
|
|
.fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
|
|
.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
|
|
.io_mem_free = &nouveau_ttm_io_mem_free,
|
|
};
|