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f43cadef2d
FW has to configure devices' StreamIDs so that SMMU is able to lookup
context and do proper translation later on. For Armada 7040 & 8040 and
publicly available FW, most of the devices are configured properly,
but some like ap_sdhci0, PCIe, NIC still remain unassigned which
results in SMMU faults about unmatched StreamID (assuming
ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y).
Since there is dependency on custom FW let SMMU be disabled by default.
People who still willing to use SMMU need to enable manually and
use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line)
with extra caution.
Fixes: 83a3545d9c ("arm64: dts: marvell: add SMMU support")
Cc: <stable@vger.kernel.org> # 5.9+
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
62 lines
1.1 KiB
Plaintext
62 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and
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* two CP110.
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*/
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#include "armada-ap806-quad.dtsi"
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#include "armada-80x0.dtsi"
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/ {
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model = "Marvell Armada 8040";
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compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp0_pcie0 {
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iommu-map =
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<0x0 &smmu 0x480 0x20>,
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<0x100 &smmu 0x4a0 0x20>,
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<0x200 &smmu 0x4c0 0x20>;
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iommu-map-mask = <0x031f>;
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};
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/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
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* in CP master is not connected (by package) to the oscillator. So
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* disable it. However, the RTC clock in CP slave is connected to the
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* oscillator so this one is let enabled.
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*/
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&cp0_rtc {
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status = "disabled";
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};
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&cp0_sata0 {
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iommus = <&smmu 0x444>;
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};
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&cp0_sdhci0 {
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iommus = <&smmu 0x445>;
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};
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&cp0_usb3_0 {
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iommus = <&smmu 0x440>;
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};
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&cp0_usb3_1 {
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iommus = <&smmu 0x441>;
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};
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&cp1_sata0 {
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iommus = <&smmu 0x454>;
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};
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&cp1_usb3_0 {
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iommus = <&smmu 0x450>;
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};
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&cp1_usb3_1 {
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iommus = <&smmu 0x451>;
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};
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