Huacai Chen 8e02c3b782 LoongArch: Add writecombine support for DMW-based ioremap() ... Currently, only TLB-based ioremap() support writecombine, so add the counterpart for DMW-based ioremap() with help of DMW2. The base address (WRITECOMBINE_BASE) is configured as 0xa000000000000000. DMW3 is unused by kernel now, however firmware may leave garbage in them and interfere kernel's address mapping. So clear it as necessary. BTW, centralize the DMW configuration to macro SETUP_DMWINS. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>		2024-07-20 22:40:59 +08:00
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hibernate_asm.S
hibernate.c
Makefile
platform.c
suspend_asm.S	LoongArch: Add writecombine support for DMW-based ioremap()	2024-07-20 22:40:59 +08:00
suspend.c	LoongArch: Give a chance to build with !CONFIG_SMP	2024-05-14 12:24:18 +08:00