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9c3b443026
Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different controller. This adds a new driver to support the regular USB PHYs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
203 lines
5.0 KiB
C
203 lines
5.0 KiB
C
/*
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* Allwinner sun9i USB phy driver
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*
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* Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
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*
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* Based on phy-sun4i-usb.c from
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* Hans de Goede <hdegoede@redhat.com>
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*
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* and code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/usb/of.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#define SUNXI_AHB_INCR16_BURST_EN BIT(11)
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#define SUNXI_AHB_INCR8_BURST_EN BIT(10)
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#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
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#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
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#define SUNXI_ULPI_BYPASS_EN BIT(0)
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/* usb1 HSIC specific bits */
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#define SUNXI_EHCI_HS_FORCE BIT(20)
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#define SUNXI_HSIC_CONNECT_DET BIT(17)
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#define SUNXI_HSIC_CONNECT_INT BIT(16)
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#define SUNXI_HSIC BIT(1)
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struct sun9i_usb_phy {
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struct phy *phy;
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void __iomem *pmu;
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struct reset_control *reset;
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struct clk *clk;
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struct clk *hsic_clk;
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enum usb_phy_interface type;
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};
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static void sun9i_usb_phy_passby(struct sun9i_usb_phy *phy, int enable)
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{
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u32 bits, reg_value;
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bits = SUNXI_AHB_INCR16_BURST_EN | SUNXI_AHB_INCR8_BURST_EN |
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SUNXI_AHB_INCR4_BURST_EN | SUNXI_AHB_INCRX_ALIGN_EN |
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SUNXI_ULPI_BYPASS_EN;
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if (phy->type == USBPHY_INTERFACE_MODE_HSIC)
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bits |= SUNXI_HSIC | SUNXI_EHCI_HS_FORCE |
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SUNXI_HSIC_CONNECT_DET | SUNXI_HSIC_CONNECT_INT;
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reg_value = readl(phy->pmu);
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if (enable)
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reg_value |= bits;
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else
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reg_value &= ~bits;
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writel(reg_value, phy->pmu);
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}
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static int sun9i_usb_phy_init(struct phy *_phy)
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{
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struct sun9i_usb_phy *phy = phy_get_drvdata(_phy);
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int ret;
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ret = clk_prepare_enable(phy->clk);
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if (ret)
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goto err_clk;
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ret = clk_prepare_enable(phy->hsic_clk);
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if (ret)
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goto err_hsic_clk;
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ret = reset_control_deassert(phy->reset);
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if (ret)
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goto err_reset;
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sun9i_usb_phy_passby(phy, 1);
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return 0;
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err_reset:
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clk_disable_unprepare(phy->hsic_clk);
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err_hsic_clk:
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clk_disable_unprepare(phy->clk);
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err_clk:
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return ret;
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}
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static int sun9i_usb_phy_exit(struct phy *_phy)
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{
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struct sun9i_usb_phy *phy = phy_get_drvdata(_phy);
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sun9i_usb_phy_passby(phy, 0);
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reset_control_assert(phy->reset);
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clk_disable_unprepare(phy->hsic_clk);
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clk_disable_unprepare(phy->clk);
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return 0;
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}
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static struct phy_ops sun9i_usb_phy_ops = {
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.init = sun9i_usb_phy_init,
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.exit = sun9i_usb_phy_exit,
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.owner = THIS_MODULE,
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};
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static int sun9i_usb_phy_probe(struct platform_device *pdev)
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{
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struct sun9i_usb_phy *phy;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct phy_provider *phy_provider;
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struct resource *res;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return -ENOMEM;
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phy->type = of_usb_get_phy_mode(np);
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if (phy->type == USBPHY_INTERFACE_MODE_HSIC) {
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phy->clk = devm_clk_get(dev, "hsic_480M");
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if (IS_ERR(phy->clk)) {
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dev_err(dev, "failed to get hsic_480M clock\n");
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return PTR_ERR(phy->clk);
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}
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phy->hsic_clk = devm_clk_get(dev, "hsic_12M");
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if (IS_ERR(phy->clk)) {
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dev_err(dev, "failed to get hsic_12M clock\n");
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return PTR_ERR(phy->clk);
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}
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phy->reset = devm_reset_control_get(dev, "hsic");
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if (IS_ERR(phy->reset)) {
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dev_err(dev, "failed to get reset control\n");
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return PTR_ERR(phy->reset);
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}
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} else {
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phy->clk = devm_clk_get(dev, "phy");
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if (IS_ERR(phy->clk)) {
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dev_err(dev, "failed to get phy clock\n");
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return PTR_ERR(phy->clk);
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}
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phy->reset = devm_reset_control_get(dev, "phy");
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if (IS_ERR(phy->reset)) {
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dev_err(dev, "failed to get reset control\n");
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return PTR_ERR(phy->reset);
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}
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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phy->pmu = devm_ioremap_resource(dev, res);
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if (IS_ERR(phy->pmu))
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return PTR_ERR(phy->pmu);
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phy->phy = devm_phy_create(dev, NULL, &sun9i_usb_phy_ops);
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if (IS_ERR(phy->phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(phy->phy);
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}
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phy_set_drvdata(phy->phy, phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id sun9i_usb_phy_of_match[] = {
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{ .compatible = "allwinner,sun9i-a80-usb-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sun9i_usb_phy_of_match);
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static struct platform_driver sun9i_usb_phy_driver = {
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.probe = sun9i_usb_phy_probe,
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.driver = {
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.of_match_table = sun9i_usb_phy_of_match,
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.name = "sun9i-usb-phy",
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}
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};
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module_platform_driver(sun9i_usb_phy_driver);
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MODULE_DESCRIPTION("Allwinner sun9i USB phy driver");
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MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
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MODULE_LICENSE("GPL");
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