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e89c5d07cd
This patch changes the clock registration code to use the s3c_register_clocks() followed by s3c_disable_clocks() instead of the loops it was using. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
421 lines
9.2 KiB
C
421 lines
9.2 KiB
C
/* linux/arch/arm/mach-s5p6442/clock.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P6442 - Clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/cpu-freq.h>
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#include <mach/regs-clock.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/pll.h>
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#include <plat/s5p-clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5p6442.h>
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static struct clksrc_clk clk_mout_apll = {
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.clk = {
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.name = "mout_apll",
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.id = -1,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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};
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static struct clksrc_clk clk_mout_mpll = {
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.clk = {
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.name = "mout_mpll",
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.id = -1,
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},
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.sources = &clk_src_mpll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_mout_epll = {
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.clk = {
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.name = "mout_epll",
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.id = -1,
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},
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.sources = &clk_src_epll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
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};
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/* Possible clock sources for ARM Mux */
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static struct clk *clk_src_arm_list[] = {
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[1] = &clk_mout_apll.clk,
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[2] = &clk_mout_mpll.clk,
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};
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static struct clksrc_sources clk_src_arm = {
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.sources = clk_src_arm_list,
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.nr_sources = ARRAY_SIZE(clk_src_arm_list),
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};
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static struct clksrc_clk clk_mout_arm = {
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.clk = {
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.name = "mout_arm",
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.id = -1,
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},
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.sources = &clk_src_arm,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
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};
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static struct clk clk_dout_a2m = {
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.name = "dout_a2m",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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};
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/* Possible clock sources for D0 Mux */
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static struct clk *clk_src_d0_list[] = {
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[1] = &clk_mout_mpll.clk,
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[2] = &clk_dout_a2m,
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};
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static struct clksrc_sources clk_src_d0 = {
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.sources = clk_src_d0_list,
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.nr_sources = ARRAY_SIZE(clk_src_d0_list),
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};
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static struct clksrc_clk clk_mout_d0 = {
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.clk = {
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.name = "mout_d0",
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.id = -1,
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},
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.sources = &clk_src_d0,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
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};
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static struct clk clk_dout_apll = {
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.name = "dout_apll",
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.id = -1,
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.parent = &clk_mout_arm.clk,
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};
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/* Possible clock sources for D0SYNC Mux */
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static struct clk *clk_src_d0sync_list[] = {
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[1] = &clk_mout_d0.clk,
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[2] = &clk_dout_apll,
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};
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static struct clksrc_sources clk_src_d0sync = {
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.sources = clk_src_d0sync_list,
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.nr_sources = ARRAY_SIZE(clk_src_d0sync_list),
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};
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static struct clksrc_clk clk_mout_d0sync = {
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.clk = {
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.name = "mout_d0sync",
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.id = -1,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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};
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/* Possible clock sources for D1 Mux */
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static struct clk *clk_src_d1_list[] = {
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[1] = &clk_mout_mpll.clk,
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[2] = &clk_dout_a2m,
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};
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static struct clksrc_sources clk_src_d1 = {
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.sources = clk_src_d1_list,
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.nr_sources = ARRAY_SIZE(clk_src_d1_list),
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};
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static struct clksrc_clk clk_mout_d1 = {
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.clk = {
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.name = "mout_d1",
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.id = -1,
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},
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.sources = &clk_src_d1,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
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};
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/* Possible clock sources for D1SYNC Mux */
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static struct clk *clk_src_d1sync_list[] = {
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[1] = &clk_mout_d1.clk,
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[2] = &clk_dout_apll,
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};
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static struct clksrc_sources clk_src_d1sync = {
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.sources = clk_src_d1sync_list,
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.nr_sources = ARRAY_SIZE(clk_src_d1sync_list),
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};
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static struct clksrc_clk clk_mout_d1sync = {
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.clk = {
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.name = "mout_d1sync",
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.id = -1,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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};
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static struct clk clk_hclkd0 = {
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.name = "hclkd0",
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.id = -1,
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.parent = &clk_mout_d0sync.clk,
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};
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static struct clk clk_hclkd1 = {
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.name = "hclkd1",
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.id = -1,
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.parent = &clk_mout_d1sync.clk,
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};
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static struct clk clk_pclkd0 = {
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.name = "pclkd0",
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.id = -1,
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.parent = &clk_hclkd0,
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};
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static struct clk clk_pclkd1 = {
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.name = "pclkd1",
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.id = -1,
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.parent = &clk_hclkd1,
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};
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int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
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}
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int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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.name = "dout_a2m",
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.id = -1,
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.parent = &clk_mout_apll.clk,
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},
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.sources = &clk_src_apll,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
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}, {
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.clk = {
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.name = "dout_apll",
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.id = -1,
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.parent = &clk_mout_arm.clk,
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},
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.sources = &clk_src_arm,
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.reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
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}, {
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.clk = {
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.name = "hclkd1",
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.id = -1,
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.parent = &clk_mout_d1sync.clk,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
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}, {
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.clk = {
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.name = "hclkd0",
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.id = -1,
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.parent = &clk_mout_d0sync.clk,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "pclkd0",
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.id = -1,
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.parent = &clk_hclkd0,
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},
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.sources = &clk_src_d0sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
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}, {
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.clk = {
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.name = "pclkd1",
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.id = -1,
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.parent = &clk_hclkd1,
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},
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.sources = &clk_src_d1sync,
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.reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
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}
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};
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/* Clock initialisation code */
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static struct clksrc_clk *init_parents[] = {
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&clk_mout_apll,
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&clk_mout_mpll,
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&clk_mout_epll,
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&clk_mout_arm,
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&clk_mout_d0,
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&clk_mout_d0sync,
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&clk_mout_d1,
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&clk_mout_d1sync,
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};
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void __init_or_cpufreq s5p6442_setup_clocks(void)
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{
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struct clk *pclkd0_clk;
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struct clk *pclkd1_clk;
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unsigned long xtal;
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unsigned long arm;
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unsigned long hclkd0 = 0;
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unsigned long hclkd1 = 0;
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unsigned long pclkd0 = 0;
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unsigned long pclkd1 = 0;
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unsigned long apll;
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unsigned long mpll;
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unsigned long epll;
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unsigned int ptr;
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printk(KERN_DEBUG "%s: registering clocks\n", __func__);
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xtal = clk_get_rate(&clk_xtal);
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printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
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apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
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s3c_set_clksrc(init_parents[ptr], true);
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_set_clksrc(&clksrcs[ptr], true);
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arm = clk_get_rate(&clk_dout_apll);
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hclkd0 = clk_get_rate(&clk_hclkd0);
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hclkd1 = clk_get_rate(&clk_hclkd1);
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pclkd0_clk = clk_get(NULL, "pclkd0");
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BUG_ON(IS_ERR(pclkd0_clk));
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pclkd0 = clk_get_rate(pclkd0_clk);
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clk_put(pclkd0_clk);
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pclkd1_clk = clk_get(NULL, "pclkd1");
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BUG_ON(IS_ERR(pclkd1_clk));
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pclkd1 = clk_get_rate(pclkd1_clk);
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clk_put(pclkd1_clk);
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printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
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hclkd0, hclkd1, pclkd0, pclkd1);
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/* For backward compatibility */
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clk_f.rate = arm;
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clk_h.rate = hclkd1;
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clk_p.rate = pclkd1;
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clk_pclkd0.rate = pclkd0;
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clk_pclkd1.rate = pclkd1;
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}
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static struct clk init_clocks_off[] = {
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{
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.name = "pdma",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip0_ctrl,
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.ctrlbit = (1 << 3),
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},
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};
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static struct clk init_clocks[] = {
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{
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.name = "systimer",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<16),
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<17),
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<18),
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<19),
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1 << 22),
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip3_ctrl,
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.ctrlbit = (1<<23),
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},
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};
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static struct clk *clks[] __initdata = {
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&clk_ext,
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&clk_epll,
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&clk_mout_apll.clk,
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&clk_mout_mpll.clk,
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&clk_mout_epll.clk,
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&clk_mout_d0.clk,
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&clk_mout_d0sync.clk,
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&clk_mout_d1.clk,
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&clk_mout_d1sync.clk,
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&clk_hclkd0,
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&clk_pclkd0,
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&clk_hclkd1,
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&clk_pclkd1,
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};
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void __init s5p6442_register_clocks(void)
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{
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_pwmclk_init();
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}
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