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ce5cad51f3
Since the commit a526973e02 ("pinctrl: mvebu: Fix mapping of pin
63 (gpo -> gpio)"), the mpp63 is no more declared as a GPO but is a
GPIO. Even if in the datasheet this pin is described as GPO, the
experience of the D-Link DNS-327L board shows that it can be used as a
GPIO.
This commits generated warnings for the board using this pin as gpo, with
this patch the dts are fixed by using the new function (gpio) instead of
the old one.
The binding documentation has also been updated accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
100 lines
5.1 KiB
Plaintext
100 lines
5.1 KiB
Plaintext
* Marvell Armada 370 SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,88f6710-pinctrl"
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- reg: register specifier of MPP registers
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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name pins functions
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================================================================================
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mpp0 0 gpio, uart0(rxd)
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mpp1 1 gpo, uart0(txd)
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mpp2 2 gpio, i2c0(sck), uart0(txd)
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mpp3 3 gpio, i2c0(sda), uart0(rxd)
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mpp4 4 gpio, vdd(cpu-pd)
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mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
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mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
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mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
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mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
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mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
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mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
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mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
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sata1(prsnt), spi1(cs1)
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mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
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audio(spdifi)
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mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
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audio(rmclk)
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mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
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spi0(cs2)
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mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
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spi0(cs3)
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mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
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mpp17 17 gpo, ge(mdc)
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mpp18 18 gpio, ge(mdio)
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mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
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mpp20 20 gpo, ge0(txd4), ge1(txd0)
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mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd)
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mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts)
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mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
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mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0)
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mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
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mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
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mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
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mpp28 28 gpio, ge0(rxd5), ge1(rxd3)
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mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
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mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
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mpp31 31 gpio, tclk, ge0(txerr)
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mpp32 32 gpio, spi0(cs0)
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mpp33 33 gpio, dev(bootcs), spi0(cs0)
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mpp34 34 gpo, dev(we0), spi0(mosi)
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mpp35 35 gpo, dev(oe), spi0(sck)
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mpp36 36 gpo, dev(a1), spi0(miso)
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mpp37 37 gpo, dev(a0), sata0(prsnt)
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mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts)
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mpp39 39 gpo, dev(ad0), audio(spdifo)
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mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts)
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mpp41 41 gpio, dev(ad2), uart1(rxd)
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mpp42 42 gpo, dev(ad3), uart1(txd)
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mpp43 43 gpo, dev(ad4), audio(bclk)
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mpp44 44 gpo, dev(ad5), audio(mclk)
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mpp45 45 gpo, dev(ad6), audio(lrclk)
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mpp46 46 gpo, dev(ad7), audio(sdo)
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mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo)
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mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
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spi0(cs1)
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mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
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audio(spdifi)
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mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
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audio(rmclk)
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mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
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mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
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mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
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pcie(clkreq1)
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mpp54 54 gpo, dev(ad15), tdm(dtx)
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mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
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sata0(prsnt)
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mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
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pcie(clkreq0), spi1(cs1)
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mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
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audio(sdo)
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mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
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uart0(rts)
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mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
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mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),
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audio(sdi)
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mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
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mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
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audio(mclk), uart0(cts)
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mpp63 63 gpio, spi0(sck), tclk
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mpp64 64 gpio, spi0(miso), spi0(cs1)
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mpp65 65 gpio, spi0(mosi), spi0(cs2)
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Note: According to the datasheet mpp63 is a gpo but there is at least
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one example of a gpio usage on the board D-Link DNS-327L
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