Linus Torvalds 498574970f RISC-V Patches for the 6.1 Merge Window, Part 2 ... * A handful of DT updates for the PolarFire SOC. * A fix to correct the handling of write-only mappings. * m{vetndor,arcd,imp}id is now in /proc/cpuinfo * The SiFive L2 cache controller support has been refactored to also support L3 caches. There's also a handful of fixes, cleanups and improvements throughout the tree. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmNJiegTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiaW+D/9nN7JMKD4KbED8MUgRVcs+TS4MQk5J QkjmAXme7w2H1+T5mxNWHk0QvEC6qMu2JQWHeott0ROYPkbXoNtuOOkzcsZhVaeb rjWH/WC5QhEeMPDc1qc0AmxVkOa937f2NkGtoEvhW6SMWvStHpefdOHo/ij106Re 7wxkcj0fjgn/zPmDltRbWSMyFZWJec5DvZ3AB4NYHnc2ycr8Z7HAG08rjZkdkIjQ zYGsCkUtrk4qShikKK3cSelW6hH1/FdM+bAo0rzt1frmTw1FLaFOsZZjOaVYekzi l0jxsb8FRBWyKBFqcagukjZwFy6D+7Q+masb0cXY03eZpEVrroA4bHiPkuZ22Ms/ 7ol/I5FvTyrj2R4zd70ziYVF3usO78t5HC4AIQmFl25TNcQdYQd8X28yh12iG6QN Pa0lh/EOr5idaT2+TErhzRepICnK1Nj9y0H5TZxYljLAhH9j0d/8+Iw88vzJnPga vek7unZ3BzkooLVIpfpkT8vC94MA0hoP849MVFQDtZgZhPMbjIkN91HrDiw9ktV2 SK9cuPndfrs5nW1WKu8F0cDziusbMHv4F51TPVRu/dFcIkspv+aLojAThgvcm42K 55LgvDgLjo7P3PUghiDXUoPZXvL19t5Bnq2/E47rlSTvvGssIu/onZO6BkxybAm6 BkHuchr8TGBWMg== =iCOr -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ...		2022-10-14 11:21:11 -07:00
..
arc	clocksource/drivers/arc_timer: Eliminate redefined macro error	2021-10-16 22:15:01 +02:00
at91	These are the pin control changes for the v6.1 kernel cycle:	2022-10-11 10:59:59 -07:00
bcm2835	firmware: raspberrypi: Add RPI_FIRMWARE_NOTIFY_DISPLAY_DONE	2022-01-11 13:16:10 +01:00
canaan	clk: Add RISC-V Canaan Kendryte K210 clock driver	2021-02-22 17:51:04 -08:00
fsl	soc: fsl: qbman: Add CGR update function	2022-09-05 14:27:39 +01:00
imx	ARM: imx: Initialize SoC ID on i.MX50	2021-05-13 15:42:21 +08:00
mediatek	memory: mtk-smi: Add enable IOMMU SMC command for MM master	2022-08-30 20:54:05 +03:00
microchip	clk: microchip: mpfs: add reset controller	2022-09-14 10:55:17 +03:00
mscc	net: dsa: felix: add support for changing DSA master	2022-09-20 10:32:36 +02:00
qcom	mfd: qcom-spmi-pmic: read fab id on supported PMICs	2022-06-18 14:01:16 +01:00
rockchip	soc: rockchip: power-domain: Manage resource conflicts with firmware	2022-05-09 03:36:52 +09:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.	2022-10-13 11:06:51 -07:00
tegra	soc/tegra: cbb: Add CBB 1.0 driver for Tegra194	2022-09-15 12:41:36 +02:00