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5c709e6998
nommu platforms do not perform address translation and therefore clearly don't have TLBs. However, some SMP code assumes the presence of the TLB flushing routines and will therefore fail to compile for a nommu system. This patch defines dummy local_* TLB operations and #defines tlb_ops_need_broadcast() as 0, therefore causing the usual ARM SMP TLB operations to call the local variants instead. Signed-off-by: Will Deacon <will.deacon@arm.com> CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> CC: Nicolas Pitre <nico@linaro.org>
74 lines
1.4 KiB
C
74 lines
1.4 KiB
C
/*
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* ARM specific SMP header, this contains our implementation
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* details.
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*/
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#ifndef __ASMARM_SMP_PLAT_H
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#define __ASMARM_SMP_PLAT_H
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#include <linux/cpumask.h>
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#include <linux/err.h>
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#include <asm/cputype.h>
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/*
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* Return true if we are running on a SMP platform
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*/
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static inline bool is_smp(void)
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{
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#ifndef CONFIG_SMP
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return false;
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#elif defined(CONFIG_SMP_ON_UP)
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extern unsigned int smp_on_up;
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return !!smp_on_up;
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#else
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return true;
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#endif
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}
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/* all SMP configurations have the extended CPUID registers */
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#ifndef CONFIG_MMU
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#define tlb_ops_need_broadcast() 0
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#else
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static inline int tlb_ops_need_broadcast(void)
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{
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if (!is_smp())
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return 0;
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return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
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}
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#endif
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#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
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#define cache_ops_need_broadcast() 0
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#else
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static inline int cache_ops_need_broadcast(void)
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{
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if (!is_smp())
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return 0;
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return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
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}
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#endif
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/*
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* Logical CPU mapping.
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*/
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extern int __cpu_logical_map[];
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#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
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/*
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* Retrieve logical cpu index corresponding to a given MPIDR[23:0]
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* - mpidr: MPIDR[23:0] to be used for the look-up
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*
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* Returns the cpu logical index or -EINVAL on look-up error
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*/
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static inline int get_logical_index(u32 mpidr)
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{
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int cpu;
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for (cpu = 0; cpu < nr_cpu_ids; cpu++)
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if (cpu_logical_map(cpu) == mpidr)
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return cpu;
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return -EINVAL;
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}
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#endif
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