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9fe6942950
This is the initial stage to transfer the pxa25x and pxa27x CPU clocks
handling from cpufreq to the clock API. More precisely, the clocks
transferred are :
- cpll : core pll, known also as the CPU core turbo frequency
- core : core, known also as the CPU actual frequency, being either the
CPU core turbo frequency or the CPU core run frequency
This transfer is a prequel to shrink the code in pxa2xx-cpufreq.c, so
that it can become, at least in devicetree builds, the casual cpufreq-dt
driver.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
508 lines
14 KiB
C
508 lines
14 KiB
C
/*
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* Marvell PXA27x family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Heavily inspired from former arch/arm/mach-pxa/clock.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk-provider.h>
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#include <mach/pxa2xx-regs.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <mach/smemc.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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enum {
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PXA_CORE_13Mhz = 0,
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PXA_CORE_RUN,
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PXA_CORE_TURBO,
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};
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enum {
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PXA_BUS_13Mhz = 0,
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PXA_BUS_RUN,
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};
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enum {
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PXA_LCD_13Mhz = 0,
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PXA_LCD_RUN,
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};
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enum {
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PXA_MEM_13Mhz = 0,
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PXA_MEM_SYSTEM_BUS,
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PXA_MEM_RUN,
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};
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#define PXA27x_CLKCFG(B, HT, T) \
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(CLKCFG_FCS | \
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((B) ? CLKCFG_FASTBUS : 0) | \
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((HT) ? CLKCFG_HALFTURBO : 0) | \
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((T) ? CLKCFG_TURBO : 0))
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#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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static const char * const get_freq_khz[] = {
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"core", "run", "cpll", "memory",
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"system_bus"
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};
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static int get_sdram_rows(void)
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{
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static int sdram_rows;
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unsigned int drac2 = 0, drac0 = 0;
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u32 mdcnfg;
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if (sdram_rows)
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return sdram_rows;
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mdcnfg = readl_relaxed(MDCNFG);
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if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
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drac2 = MDCNFG_DRAC2(mdcnfg);
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if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
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drac0 = MDCNFG_DRAC0(mdcnfg);
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sdram_rows = 1 << (11 + max(drac0, drac2));
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return sdram_rows;
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}
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static u32 mdrefr_dri(unsigned int freq_khz)
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{
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u32 interval = freq_khz * SDRAM_TREF / get_sdram_rows();
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return (interval - 31) / 32;
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}
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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struct clk *clk;
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unsigned long clks[5];
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int i;
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for (i = 0; i < 5; i++) {
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clk = clk_get(NULL, get_freq_khz[i]);
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if (IS_ERR(clk)) {
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clks[i] = 0;
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} else {
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clks[i] = clk_get_rate(clk);
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clk_put(clk);
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}
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}
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if (info) {
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pr_info("Run Mode clock: %ld.%02ldMHz\n",
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clks[1] / 1000000, (clks[1] % 1000000) / 10000);
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pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
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clks[2] / 1000000, (clks[2] % 1000000) / 10000);
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pr_info("Memory clock: %ld.%02ldMHz\n",
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clks[3] / 1000000, (clks[3] % 1000000) / 10000);
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pr_info("System bus clock: %ld.%02ldMHz\n",
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clks[4] / 1000000, (clks[4] % 1000000) / 10000);
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}
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return (unsigned int)clks[0] / KHz;
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}
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bool pxa27x_is_ppll_disabled(void)
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{
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unsigned long ccsr = readl(CCSR);
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return ccsr & (1 << CCCR_PPDIS_BIT);
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}
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#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
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bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
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is_lp, CKEN, CKEN_ ## bit, flags)
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#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
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PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
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div_hp, bit, pxa27x_is_ppll_disabled, 0)
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PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
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PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
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PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
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PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
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PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
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#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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CKEN, CKEN_ ## bit, 0)
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#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
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static struct desc_clk_cken pxa27x_clocks[] __initdata = {
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PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
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PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
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PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
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PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
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PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
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PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
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PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
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PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
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PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
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PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
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PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
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PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
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PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
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PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
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pxa27x_32Mhz_bus_parents, 0),
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PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
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PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
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PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
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pxa27x_lcd_bus_parents, 0),
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PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
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pxa27x_membus_parents, 0),
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};
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/*
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* PXA270 definitions
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*
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* For the PXA27x:
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* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
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*
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* A = 0 => memory controller clock from table 3-7,
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* A = 1 => memory controller clock = system bus clock
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* Run mode frequency = 13 MHz * L
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* Turbo mode frequency = 13 MHz * L * N
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* System bus frequency = 13 MHz * L / (B + 1)
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*
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* In CCCR:
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* A = 1
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* L = 16 oscillator to run mode ratio
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* 2N = 6 2 * (turbo mode to run mode ratio)
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*
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* In CCLKCFG:
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* B = 1 Fast bus mode
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* HT = 0 Half-Turbo mode
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* T = 1 Turbo mode
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*
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* For now, just support some of the combinations in table 3-7 of
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* PXA27x Processor Family Developer's Manual to simplify frequency
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* change sequences.
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*/
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static struct pxa2xx_freq pxa27x_freqs[] = {
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{104000000, 104000, PXA27x_CCCR(1, 8, 2), 0, PXA27x_CLKCFG(1, 0, 1) },
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{156000000, 104000, PXA27x_CCCR(1, 8, 3), 0, PXA27x_CLKCFG(1, 0, 1) },
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{208000000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CLKCFG(0, 0, 1) },
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{312000000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CLKCFG(1, 0, 1) },
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{416000000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CLKCFG(1, 0, 1) },
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{520000000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CLKCFG(1, 0, 1) },
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{624000000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CLKCFG(1, 0, 1) },
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};
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static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg;
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unsigned int t, ht;
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unsigned int l, L, n2, N;
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unsigned long ccsr = readl(CCSR);
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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l = ccsr & CCSR_L_MASK;
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n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
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L = l * parent_rate;
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N = (L * n2) / 2;
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return N;
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}
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static int clk_pxa27x_cpll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return pxa2xx_determine_rate(req, pxa27x_freqs,
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ARRAY_SIZE(pxa27x_freqs));
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}
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static int clk_pxa27x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int i;
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pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
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for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
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if (pxa27x_freqs[i].cpll == rate)
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break;
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if (i >= ARRAY_SIZE(pxa27x_freqs))
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return -EINVAL;
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pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR);
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return 0;
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}
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PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
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RATE_OPS(clk_pxa27x_cpll, "cpll");
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static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned int l, osc_forced;
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unsigned long ccsr = readl(CCSR);
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unsigned long cccr = readl(CCCR);
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l = ccsr & CCSR_L_MASK;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced) {
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if (cccr & (1 << CCCR_LCD_26_BIT))
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return parent_rate * 2;
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else
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return parent_rate;
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}
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if (l <= 7)
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return parent_rate;
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if (l <= 16)
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return parent_rate / 2;
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return parent_rate / 4;
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}
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static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
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{
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unsigned int osc_forced;
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unsigned long ccsr = readl(CCSR);
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_LCD_13Mhz;
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else
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return PXA_LCD_RUN;
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}
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PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
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static void __init pxa27x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE,
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13 * MHz);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE,
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32768 * KHz);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
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}
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static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
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{
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unsigned long clkcfg;
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unsigned int t, ht, osc_forced;
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unsigned long ccsr = readl(CCSR);
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_CORE_13Mhz;
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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if (ht || t)
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return PXA_CORE_TURBO;
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return PXA_CORE_RUN;
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}
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static int clk_pxa27x_core_set_parent(struct clk_hw *hw, u8 index)
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{
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if (index > PXA_CORE_TURBO)
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return -EINVAL;
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pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
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return 0;
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}
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static int clk_pxa27x_core_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return __clk_mux_determine_rate(hw, req);
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}
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PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
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MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
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static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long ccsr = readl(CCSR);
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unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
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return (parent_rate / n2) * 2;
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}
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PARENTS(clk_pxa27x_run) = { "cpll" };
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RATE_RO_OPS(clk_pxa27x_run, "run");
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static void __init pxa27x_register_core(void)
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{
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clkdev_pxa_register(CLK_NONE, "cpll", NULL,
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clk_register_clk_pxa27x_cpll());
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clkdev_pxa_register(CLK_NONE, "run", NULL,
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clk_register_clk_pxa27x_run());
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clkdev_pxa_register(CLK_CORE, "core", NULL,
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clk_register_clk_pxa27x_core());
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}
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static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg;
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unsigned int b, osc_forced;
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unsigned long ccsr = readl(CCSR);
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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b = clkcfg & (1 << 3);
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if (osc_forced)
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return parent_rate;
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if (b)
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return parent_rate;
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else
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return parent_rate / 2;
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}
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static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
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{
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unsigned int osc_forced;
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unsigned long ccsr = readl(CCSR);
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_BUS_13Mhz;
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else
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return PXA_BUS_RUN;
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}
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PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
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static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
|
|
{
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|
unsigned int a, l, osc_forced;
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|
unsigned long cccr = readl(CCCR);
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|
unsigned long ccsr = readl(CCSR);
|
|
|
|
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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|
a = cccr & (1 << CCCR_A_BIT);
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|
l = ccsr & CCSR_L_MASK;
|
|
|
|
if (osc_forced || a)
|
|
return parent_rate;
|
|
if (l <= 10)
|
|
return parent_rate;
|
|
if (l <= 20)
|
|
return parent_rate / 2;
|
|
return parent_rate / 4;
|
|
}
|
|
|
|
static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
|
|
{
|
|
unsigned int osc_forced, a;
|
|
unsigned long cccr = readl(CCCR);
|
|
unsigned long ccsr = readl(CCSR);
|
|
|
|
osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
|
|
a = cccr & (1 << CCCR_A_BIT);
|
|
if (osc_forced)
|
|
return PXA_MEM_13Mhz;
|
|
if (a)
|
|
return PXA_MEM_SYSTEM_BUS;
|
|
else
|
|
return PXA_MEM_RUN;
|
|
}
|
|
|
|
PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
|
|
MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
|
|
|
|
#define DUMMY_CLK(_con_id, _dev_id, _parent) \
|
|
{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
|
|
struct dummy_clk {
|
|
const char *con_id;
|
|
const char *dev_id;
|
|
const char *parent;
|
|
};
|
|
static struct dummy_clk dummy_clks[] __initdata = {
|
|
DUMMY_CLK(NULL, "pxa27x-gpio", "osc_32_768khz"),
|
|
DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
|
|
DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
|
|
};
|
|
|
|
static void __init pxa27x_dummy_clocks_init(void)
|
|
{
|
|
struct clk *clk;
|
|
struct dummy_clk *d;
|
|
const char *name;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
|
|
d = &dummy_clks[i];
|
|
name = d->dev_id ? d->dev_id : d->con_id;
|
|
clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
|
|
clk_register_clkdev(clk, d->con_id, d->dev_id);
|
|
}
|
|
}
|
|
|
|
static void __init pxa27x_base_clocks_init(void)
|
|
{
|
|
pxa27x_register_plls();
|
|
pxa27x_register_core();
|
|
clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
|
|
clk_register_clk_pxa27x_system_bus());
|
|
clkdev_pxa_register(CLK_NONE, "memory", NULL,
|
|
clk_register_clk_pxa27x_memory());
|
|
clk_register_clk_pxa27x_lcd_base();
|
|
}
|
|
|
|
int __init pxa27x_clocks_init(void)
|
|
{
|
|
pxa27x_base_clocks_init();
|
|
pxa27x_dummy_clocks_init();
|
|
return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
|
|
}
|
|
|
|
static void __init pxa27x_dt_clocks_init(struct device_node *np)
|
|
{
|
|
pxa27x_clocks_init();
|
|
clk_pxa_dt_common_init(np);
|
|
}
|
|
CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
|