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6891dd25d3
Loading firmware when actually bringing eth device up. This also will allow driver to be insmoded when filesystem with firmware files is not available yet. Suggested by Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
662 lines
16 KiB
C
662 lines
16 KiB
C
/* bnx2x_cmn.h: Broadcom Everest network driver.
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*
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* Copyright (c) 2007-2010 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Based on code from Michael Chan's bnx2 driver
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* UDP CSUM errata workaround by Arik Gendelman
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* Slowpath and fastpath rework by Vladislav Zolotarov
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* Statistics and Link management by Yitchak Gertner
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*
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*/
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#ifndef BNX2X_CMN_H
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#define BNX2X_CMN_H
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#include <linux/types.h>
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#include <linux/netdevice.h>
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#include "bnx2x.h"
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/*********************** Interfaces ****************************
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* Functions that need to be implemented by each driver version
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*/
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/**
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* Initialize link parameters structure variables.
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*
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* @param bp
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* @param load_mode
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*
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* @return u8
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*/
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u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
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/**
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* Configure hw according to link parameters structure.
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*
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* @param bp
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*/
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void bnx2x_link_set(struct bnx2x *bp);
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/**
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* Query link status
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*
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* @param bp
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*
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* @return 0 - link is UP
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*/
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u8 bnx2x_link_test(struct bnx2x *bp);
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/**
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* Handles link status change
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*
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* @param bp
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*/
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void bnx2x__link_status_update(struct bnx2x *bp);
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/**
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* MSI-X slowpath interrupt handler
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*
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* @param irq
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* @param dev_instance
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*
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* @return irqreturn_t
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*/
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irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
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/**
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* non MSI-X interrupt handler
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*
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* @param irq
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* @param dev_instance
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*
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* @return irqreturn_t
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*/
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irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
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#ifdef BCM_CNIC
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/**
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* Send command to cnic driver
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*
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* @param bp
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* @param cmd
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*/
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int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
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/**
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* Provides cnic information for proper interrupt handling
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*
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* @param bp
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*/
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void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
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#endif
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/**
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* Enable HW interrupts.
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*
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* @param bp
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*/
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void bnx2x_int_enable(struct bnx2x *bp);
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/**
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* Disable interrupts. This function ensures that there are no
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* ISRs or SP DPCs (sp_task) are running after it returns.
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*
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* @param bp
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* @param disable_hw if true, disable HW interrupts.
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*/
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void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
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/**
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* Loads device firmware
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_init_firmware(struct bnx2x *bp);
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/**
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* Init HW blocks according to current initialization stage:
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* COMMON, PORT or FUNCTION.
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*
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* @param bp
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* @param load_code: COMMON, PORT or FUNCTION
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*
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* @return int
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*/
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int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
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/**
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* Init driver internals:
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* - rings
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* - status blocks
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* - etc.
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*
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* @param bp
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* @param load_code COMMON, PORT or FUNCTION
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*/
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void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
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/**
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* Allocate driver's memory.
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_alloc_mem(struct bnx2x *bp);
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/**
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* Release driver's memory.
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*
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* @param bp
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*/
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void bnx2x_free_mem(struct bnx2x *bp);
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/**
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* Bring up a leading (the first) eth Client.
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_setup_leading(struct bnx2x *bp);
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/**
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* Setup non-leading eth Client.
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*
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* @param bp
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* @param fp
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*
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* @return int
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*/
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int bnx2x_setup_multi(struct bnx2x *bp, int index);
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/**
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* Set number of quueus according to mode and number of available
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* msi-x vectors
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*
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* @param bp
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*
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*/
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void bnx2x_set_num_queues_msix(struct bnx2x *bp);
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/**
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* Cleanup chip internals:
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* - Cleanup MAC configuration.
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* - Close clients.
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* - etc.
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*
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* @param bp
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* @param unload_mode
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*/
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void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
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/**
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* Acquire HW lock.
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*
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* @param bp
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* @param resource Resource bit which was locked
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*
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* @return int
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*/
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int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
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/**
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* Release HW lock.
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*
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* @param bp driver handle
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* @param resource Resource bit which was locked
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*
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* @return int
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*/
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int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
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/**
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* Configure eth MAC address in the HW according to the value in
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* netdev->dev_addr for 57711
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*
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* @param bp driver handle
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* @param set
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*/
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void bnx2x_set_eth_mac_addr_e1h(struct bnx2x *bp, int set);
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/**
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* Configure eth MAC address in the HW according to the value in
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* netdev->dev_addr for 57710
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*
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* @param bp driver handle
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* @param set
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*/
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void bnx2x_set_eth_mac_addr_e1(struct bnx2x *bp, int set);
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#ifdef BCM_CNIC
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/**
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* Set iSCSI MAC(s) at the next enties in the CAM after the ETH
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* MAC(s). The function will wait until the ramrod completion
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* returns.
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*
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* @param bp driver handle
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* @param set set or clear the CAM entry
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*
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* @return 0 if cussess, -ENODEV if ramrod doesn't return.
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*/
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int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set);
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#endif
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/**
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* Initialize status block in FW and HW
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*
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* @param bp driver handle
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* @param sb host_status_block
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* @param dma_addr_t mapping
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* @param int sb_id
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*/
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void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
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dma_addr_t mapping, int sb_id);
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/**
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* Reconfigure FW/HW according to dev->flags rx mode
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*
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* @param dev net_device
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*
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*/
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void bnx2x_set_rx_mode(struct net_device *dev);
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/**
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* Configure MAC filtering rules in a FW.
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*
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* @param bp driver handle
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*/
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void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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/* Parity errors related */
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void bnx2x_inc_load_cnt(struct bnx2x *bp);
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u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
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bool bnx2x_chk_parity_attn(struct bnx2x *bp);
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bool bnx2x_reset_is_done(struct bnx2x *bp);
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void bnx2x_disable_close_the_gate(struct bnx2x *bp);
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/**
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* Perform statistics handling according to event
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*
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* @param bp driver handle
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* @param even tbnx2x_stats_event
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*/
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void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
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/**
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* Configures FW with client paramteres (like HW VLAN removal)
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* for each active client.
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*
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* @param bp
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*/
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void bnx2x_set_client_config(struct bnx2x *bp);
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/**
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* Handle sp events
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*
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* @param fp fastpath handle for the event
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* @param rr_cqe eth_rx_cqe
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*/
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void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
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static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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{
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struct host_status_block *fpsb = fp->status_blk;
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barrier(); /* status block is written to by the chip */
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fp->fp_c_idx = fpsb->c_status_block.status_block_index;
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fp->fp_u_idx = fpsb->u_status_block.status_block_index;
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}
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static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
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struct bnx2x_fastpath *fp,
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u16 bd_prod, u16 rx_comp_prod,
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u16 rx_sge_prod)
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{
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struct ustorm_eth_rx_producers rx_prods = {0};
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int i;
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/* Update producers */
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rx_prods.bd_prod = bd_prod;
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rx_prods.cqe_prod = rx_comp_prod;
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rx_prods.sge_prod = rx_sge_prod;
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/*
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* Make sure that the BD and SGE data is updated before updating the
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* producers since FW might read the BD/SGE right after the producer
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* is updated.
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* This is only applicable for weak-ordered memory model archs such
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* as IA-64. The following barrier is also mandatory since FW will
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* assumes BDs must have buffers.
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*/
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wmb();
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for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
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REG_WR(bp, BAR_USTRORM_INTMEM +
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USTORM_RX_PRODS_OFFSET(BP_PORT(bp), fp->cl_id) + i*4,
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((u32 *)&rx_prods)[i]);
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mmiowb(); /* keep prod updates ordered */
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DP(NETIF_MSG_RX_STATUS,
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"queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
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fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
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}
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static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
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u8 storm, u16 index, u8 op, u8 update)
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{
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u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
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COMMAND_REG_INT_ACK);
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struct igu_ack_register igu_ack;
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igu_ack.status_block_index = index;
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igu_ack.sb_id_and_flags =
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((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
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(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
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(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
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(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
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DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
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(*(u32 *)&igu_ack), hc_addr);
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REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
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/* Make sure that ACK is written */
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mmiowb();
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barrier();
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}
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static inline u16 bnx2x_ack_int(struct bnx2x *bp)
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{
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u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
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COMMAND_REG_SIMD_MASK);
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u32 result = REG_RD(bp, hc_addr);
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DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
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result, hc_addr);
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return result;
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}
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/*
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* fast path service functions
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*/
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static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
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{
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/* Tell compiler that consumer and producer can change */
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barrier();
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return (fp->tx_pkt_prod != fp->tx_pkt_cons);
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}
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static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
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{
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s16 used;
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u16 prod;
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u16 cons;
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prod = fp->tx_bd_prod;
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cons = fp->tx_bd_cons;
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/* NUM_TX_RINGS = number of "next-page" entries
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It will be used as a threshold */
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used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
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#ifdef BNX2X_STOP_ON_ERROR
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WARN_ON(used < 0);
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WARN_ON(used > fp->bp->tx_ring_size);
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WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
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#endif
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return (s16)(fp->bp->tx_ring_size) - used;
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}
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static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
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{
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u16 hw_cons;
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/* Tell compiler that status block fields can change */
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barrier();
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hw_cons = le16_to_cpu(*fp->tx_cons_sb);
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return hw_cons != fp->tx_pkt_cons;
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}
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static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
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struct bnx2x_fastpath *fp, u16 index)
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{
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struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
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struct page *page = sw_buf->page;
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struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
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/* Skip "next page" elements */
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if (!page)
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return;
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dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
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SGE_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
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__free_pages(page, PAGES_PER_SGE_SHIFT);
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sw_buf->page = NULL;
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sge->addr_hi = 0;
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sge->addr_lo = 0;
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}
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static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
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struct bnx2x_fastpath *fp, int last)
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{
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int i;
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for (i = 0; i < last; i++)
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bnx2x_free_rx_sge(bp, fp, i);
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}
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static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
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struct bnx2x_fastpath *fp, u16 index)
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{
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struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
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struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
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struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
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dma_addr_t mapping;
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if (unlikely(page == NULL))
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return -ENOMEM;
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mapping = dma_map_page(&bp->pdev->dev, page, 0,
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SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
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__free_pages(page, PAGES_PER_SGE_SHIFT);
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return -ENOMEM;
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}
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sw_buf->page = page;
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dma_unmap_addr_set(sw_buf, mapping, mapping);
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sge->addr_hi = cpu_to_le32(U64_HI(mapping));
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sge->addr_lo = cpu_to_le32(U64_LO(mapping));
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return 0;
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}
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static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
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struct bnx2x_fastpath *fp, u16 index)
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{
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struct sk_buff *skb;
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struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
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struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
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dma_addr_t mapping;
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skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
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if (unlikely(skb == NULL))
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return -ENOMEM;
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mapping = dma_map_single(&bp->pdev->dev, skb->data, bp->rx_buf_size,
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
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dev_kfree_skb(skb);
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return -ENOMEM;
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}
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rx_buf->skb = skb;
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dma_unmap_addr_set(rx_buf, mapping, mapping);
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rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
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rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
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return 0;
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}
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/* note that we are not allocating a new skb,
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* we are just moving one from cons to prod
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* we are not creating a new mapping,
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* so there is no need to check for dma_mapping_error().
|
|
*/
|
|
static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
|
|
struct sk_buff *skb, u16 cons, u16 prod)
|
|
{
|
|
struct bnx2x *bp = fp->bp;
|
|
struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
|
|
struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
|
|
struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
|
|
struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
|
|
|
|
dma_sync_single_for_device(&bp->pdev->dev,
|
|
dma_unmap_addr(cons_rx_buf, mapping),
|
|
RX_COPY_THRESH, DMA_FROM_DEVICE);
|
|
|
|
prod_rx_buf->skb = cons_rx_buf->skb;
|
|
dma_unmap_addr_set(prod_rx_buf, mapping,
|
|
dma_unmap_addr(cons_rx_buf, mapping));
|
|
*prod_bd = *cons_bd;
|
|
}
|
|
|
|
static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
|
|
int idx = RX_SGE_CNT * i - 1;
|
|
|
|
for (j = 0; j < 2; j++) {
|
|
SGE_MASK_CLEAR_BIT(fp, idx);
|
|
idx--;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
|
|
{
|
|
/* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
|
|
memset(fp->sge_mask, 0xff,
|
|
(NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
|
|
|
|
/* Clear the two last indices in the page to 1:
|
|
these are the indices that correspond to the "next" element,
|
|
hence will never be indicated and should be removed from
|
|
the calculations. */
|
|
bnx2x_clear_sge_mask_next_elems(fp);
|
|
}
|
|
static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, int last)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < last; i++) {
|
|
struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
|
|
struct sk_buff *skb = rx_buf->skb;
|
|
|
|
if (skb == NULL) {
|
|
DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
|
|
continue;
|
|
}
|
|
|
|
if (fp->tpa_state[i] == BNX2X_TPA_START)
|
|
dma_unmap_single(&bp->pdev->dev,
|
|
dma_unmap_addr(rx_buf, mapping),
|
|
bp->rx_buf_size, DMA_FROM_DEVICE);
|
|
|
|
dev_kfree_skb(skb);
|
|
rx_buf->skb = NULL;
|
|
}
|
|
}
|
|
|
|
|
|
static inline void bnx2x_init_tx_ring(struct bnx2x *bp)
|
|
{
|
|
int i, j;
|
|
|
|
for_each_queue(bp, j) {
|
|
struct bnx2x_fastpath *fp = &bp->fp[j];
|
|
|
|
for (i = 1; i <= NUM_TX_RINGS; i++) {
|
|
struct eth_tx_next_bd *tx_next_bd =
|
|
&fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
|
|
|
|
tx_next_bd->addr_hi =
|
|
cpu_to_le32(U64_HI(fp->tx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
|
|
tx_next_bd->addr_lo =
|
|
cpu_to_le32(U64_LO(fp->tx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
|
|
}
|
|
|
|
fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
|
|
fp->tx_db.data.zero_fill1 = 0;
|
|
fp->tx_db.data.prod = 0;
|
|
|
|
fp->tx_pkt_prod = 0;
|
|
fp->tx_pkt_cons = 0;
|
|
fp->tx_bd_prod = 0;
|
|
fp->tx_bd_cons = 0;
|
|
fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
|
|
fp->tx_pkt = 0;
|
|
}
|
|
}
|
|
static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
|
|
{
|
|
u16 rx_cons_sb;
|
|
|
|
/* Tell compiler that status block fields can change */
|
|
barrier();
|
|
rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
|
|
if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
|
|
rx_cons_sb++;
|
|
return (fp->rx_comp_cons != rx_cons_sb);
|
|
}
|
|
|
|
/* HW Lock for shared dual port PHYs */
|
|
void bnx2x_acquire_phy_lock(struct bnx2x *bp);
|
|
void bnx2x_release_phy_lock(struct bnx2x *bp);
|
|
|
|
void bnx2x_link_report(struct bnx2x *bp);
|
|
int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
|
|
int bnx2x_tx_int(struct bnx2x_fastpath *fp);
|
|
void bnx2x_init_rx_rings(struct bnx2x *bp);
|
|
netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
|
|
|
|
int bnx2x_change_mac_addr(struct net_device *dev, void *p);
|
|
void bnx2x_tx_timeout(struct net_device *dev);
|
|
void bnx2x_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp);
|
|
void bnx2x_netif_start(struct bnx2x *bp);
|
|
void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
|
|
void bnx2x_free_irq(struct bnx2x *bp, bool disable_only);
|
|
int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
|
|
int bnx2x_resume(struct pci_dev *pdev);
|
|
void bnx2x_free_skbs(struct bnx2x *bp);
|
|
int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
|
|
int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
|
|
int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
|
|
int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
|
|
|
|
#endif /* BNX2X_CMN_H */
|