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The Haswell Power Control Unit has a non-PCI register (CONFIG_TDP_NOMINAL) where BAR 0 is supposed to be. This is erratum HSE43 in the spec update referenced below: The PCIe* Base Specification indicates that Configuration Space Headers have a base address register at offset 0x10. Due to this erratum, the Power Control Unit's CONFIG_TDP_NOMINAL CSR (Bus 1; Device 30; Function 3; Offset 0x10) is located where a base register is expected. Mark the PCU as having non-compliant BARs so we don't try to probe any of them. There are no other BARs on this device. Rename the quirk so it's not Broadwell-specific. Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-datasheet-vol-2.html (section 5.4, Device 30 Function 3) Link: https://bugzilla.kernel.org/show_bug.cgi?id=153881 Reported-by: Paul Menzel <pmenzel@molgen.mpg.de> Tested-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Myron Stowe <myron.stowe@redhat.com> |
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| .. | ||
| acpi.c | ||
| amd_bus.c | ||
| broadcom_bus.c | ||
| bus_numa.c | ||
| bus_numa.h | ||
| ce4100.c | ||
| common.c | ||
| direct.c | ||
| early.c | ||
| fixup.c | ||
| i386.c | ||
| init.c | ||
| intel_mid_pci.c | ||
| irq.c | ||
| legacy.c | ||
| Makefile | ||
| mmconfig_32.c | ||
| mmconfig_64.c | ||
| mmconfig-shared.c | ||
| numachip.c | ||
| olpc.c | ||
| pcbios.c | ||
| sta2x11-fixup.c | ||
| vmd.c | ||
| xen.c | ||