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This driver works by adjusting the divider on the DRAM controller's module clock. Thus there is no fixed set of OPPs, only "full speed" down to "quarter speed" (or whatever the maximum divider is on that variant). It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which takes care of updating registers during the critical section while DRAM is inaccessible. This driver should support several sunxi SoCs, starting with the A33, which have a DesignWare DDR3 controller with merged PHY register space and the matching MBUS register layout (so not A63 or later). However, the driver has only been tested on the A64/H5, so those are the only compatibles enabled for now. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> |
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| .. | ||
| event | ||
| devfreq-event.c | ||
| devfreq.c | ||
| exynos-bus.c | ||
| governor_passive.c | ||
| governor_performance.c | ||
| governor_powersave.c | ||
| governor_simpleondemand.c | ||
| governor_userspace.c | ||
| governor.h | ||
| imx8m-ddrc.c | ||
| imx-bus.c | ||
| Kconfig | ||
| Makefile | ||
| rk3399_dmc.c | ||
| sun8i-a33-mbus.c | ||
| tegra30-devfreq.c | ||