Christoph Hellwig 8bf90f320d riscv: implement remote sfence.i using IPIs ... The RISC-V ISA only supports flushing the instruction cache for the local CPU core. Currently we always offload the remote TLB flushing to the SBI, which then issues an IPI under the hoods. But with M-mode we do not have an SBI so we have to do it ourselves. IPI to the other nodes using the existing kernel helpers instead if we have native clint support and thus can IPI directly from the kernel. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: cleaned up code comment] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-13 13:24:21 -08:00
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cacheflush.c	riscv: implement remote sfence.i using IPIs	2019-11-13 13:24:21 -08:00
context.c	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
extable.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
fault.c	riscv: abstract out CSR names for supervisor vs machine mode	2019-11-05 09:20:42 -08:00
hugetlbpage.c	riscv: Introduce huge page support for 32/64bit kernel	2019-07-03 15:23:38 -07:00
init.c	riscv: init: merge split string literals in preprocessor directive	2019-10-28 00:46:01 -07:00
ioremap.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	2019-06-05 17:36:37 +02:00
Makefile	riscv: move the TLB flush logic out of line	2019-09-05 01:54:51 -07:00
sifive_l2_cache.c	riscv: mark some code and data as file-static	2019-10-28 00:46:01 -07:00
tlbflush.c	riscv: move the TLB flush logic out of line	2019-09-05 01:54:51 -07:00