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34b8c66173
Add support for the QSPI controller found some on Freescale/Motorola Coldfire MCUs. Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are supported. The hardware drives the MISO, MOSI and SCLK lines, but the chip selects are managed via GPIO and must be configured by the board code. The QSPI controller has an 80 byte buffer which allows us to transfer up to 16 words at a time. For transfers longer than 16 words, we split the buffer in half so we can update in one half while the controller is operating on the other half. Interrupt latencies then ultimately limits our sustained thru-put to something less than half the maximum speed supported by the part. Signed-off-by: Steven King <sfking@fdwdc.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
64 lines
2.2 KiB
Makefile
64 lines
2.2 KiB
Makefile
#
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# Makefile for kernel SPI drivers.
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#
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ifeq ($(CONFIG_SPI_DEBUG),y)
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EXTRA_CFLAGS += -DDEBUG
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endif
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# small core, mostly translating board-specific
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# config declarations into driver model code
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obj-$(CONFIG_SPI_MASTER) += spi.o
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# SPI master controller drivers (bus)
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obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o
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obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o
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obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPI_COLDFIRE_QSPI) += coldfire_qspi.o
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obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
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obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
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obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
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obj-$(CONFIG_SPI_OMAP_UWIRE) += omap_uwire.o
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obj-$(CONFIG_SPI_OMAP24XX) += omap2_mcspi.o
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obj-$(CONFIG_SPI_OMAP_100K) += omap_spi_100k.o
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obj-$(CONFIG_SPI_ORION) += orion_spi.o
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obj-$(CONFIG_SPI_PL022) += amba-pl022.o
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obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
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obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
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obj-$(CONFIG_SPI_MPC8xxx) += spi_mpc8xxx.o
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obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
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obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx_hw.o
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obj-$(CONFIG_SPI_S3C64XX) += spi_s3c64xx.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_XILINX_OF) += xilinx_spi_of.o
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obj-$(CONFIG_SPI_XILINX_PLTFM) += xilinx_spi_pltfm.o
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obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
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# special build for s3c24xx spi driver with fiq support
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spi_s3c24xx_hw-y := spi_s3c24xx.o
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spi_s3c24xx_hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi_s3c24xx_fiq.o
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# ... add above this line ...
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# SPI protocol drivers (device/link on bus)
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obj-$(CONFIG_SPI_SPIDEV) += spidev.o
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obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o
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# ... add above this line ...
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# SPI slave controller drivers (upstream link)
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# ... add above this line ...
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# SPI slave drivers (protocol for that link)
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# ... add above this line ...
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