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980f2296b5
This updates the IOP platform to use the kernel's generic time framework. With clockevent support in place, this reduces to selecting GENERIC_TIME and removing the platform's private timer ->offset() operation (iop_gettimeoffset). Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
124 lines
2.7 KiB
C
124 lines
2.7 KiB
C
#ifndef _IOP13XX_TIME_H_
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#define _IOP13XX_TIME_H_
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#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
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#define IOP_TMR_EN 0x02
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#define IOP_TMR_RELOAD 0x04
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#define IOP_TMR_PRIVILEGED 0x08
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#define IOP_TMR_RATIO_1_1 0x00
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#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
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#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
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#define IOP13XX_CORE_FREQ_MASK (7 << 16)
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#define IOP13XX_CORE_FREQ_600 (0 << 16)
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#define IOP13XX_CORE_FREQ_667 (1 << 16)
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#define IOP13XX_CORE_FREQ_800 (2 << 16)
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#define IOP13XX_CORE_FREQ_933 (3 << 16)
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#define IOP13XX_CORE_FREQ_1000 (4 << 16)
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#define IOP13XX_CORE_FREQ_1200 (5 << 16)
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void iop_init_time(unsigned long tickrate);
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static inline unsigned long iop13xx_core_freq(void)
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{
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unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
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freq &= IOP13XX_CORE_FREQ_MASK;
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switch (freq) {
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case IOP13XX_CORE_FREQ_600:
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return 600000000;
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case IOP13XX_CORE_FREQ_667:
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return 667000000;
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case IOP13XX_CORE_FREQ_800:
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return 800000000;
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case IOP13XX_CORE_FREQ_933:
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return 933000000;
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case IOP13XX_CORE_FREQ_1000:
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return 1000000000;
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case IOP13XX_CORE_FREQ_1200:
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return 1200000000;
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default:
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printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
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__func__);
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}
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return 800000000;
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}
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static inline unsigned long iop13xx_xsi_bus_ratio(void)
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{
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unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
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ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
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switch (ratio) {
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case IOP13XX_XSI_FREQ_RATIO_2:
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return 2;
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case IOP13XX_XSI_FREQ_RATIO_3:
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return 3;
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case IOP13XX_XSI_FREQ_RATIO_4:
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return 4;
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default:
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printk("%s: warning unknown ratio, defaulting to 2\n",
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__func__);
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}
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return 2;
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}
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static inline u32 read_tmr0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
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return val;
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}
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static inline void write_tmr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
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}
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static inline void write_tmr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
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}
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static inline u32 read_tcr0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
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return val;
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}
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static inline void write_tcr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
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}
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static inline u32 read_tcr1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
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return val;
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}
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static inline void write_tcr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
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}
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static inline void write_trr0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
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}
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static inline void write_trr1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
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}
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static inline void write_tisr(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
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}
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#endif
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