Peter Zijlstra 8b549c18ae openrisc: Define memory barrier mb ... This came up in the discussion of the requirements of qspinlock on an architecture. OpenRISC uses qspinlock, but it was noticed that the memmory barrier was not defined. Peter defined it in the mail thread writing: As near as I can tell this should do. The arch spec only lists this one instruction and the text makes it sound like a completion barrier. This is correct so applying this patch. Signed-off-by: Peter Zijlstra <peterz@infradead.org> [shorne@gmail.com:Turned the mail into a patch] Signed-off-by: Stafford Horne <shorne@gmail.com>		2021-05-15 16:00:10 +09:00
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asm	openrisc: Define memory barrier mb	2021-05-15 16:00:10 +09:00
uapi/asm	openrisc: Enable the clone3 syscall	2020-03-02 18:10:52 +09:00