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affb72c3a8
Now, a dedicated HEST tabling parsing code is used for PCIE AER firmware_first setup. It is rebased on general HEST tabling parsing code of APEI. The firmware_first setup code is moved from PCI core to AER driver too, because it is only AER related. Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Len Brown <len.brown@intel.com>
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
/*
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* Access ACPI _OSC method
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*
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* Copyright (C) 2006 Intel Corp.
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* Tom Long Nguyen (tom.l.nguyen@intel.com)
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* Zhang Yanmin (yanmin.zhang@intel.com)
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*
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/acpi.h>
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#include <linux/pci-acpi.h>
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#include <linux/delay.h>
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#include <acpi/apei.h>
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#include "aerdrv.h"
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/**
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* aer_osc_setup - run ACPI _OSC method
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* @pciedev: pcie_device which AER is being enabled on
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*
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* @return: Zero on success. Nonzero otherwise.
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*
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* Invoked when PCIe bus loads AER service driver. To avoid conflict with
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* BIOS AER support requires BIOS to yield AER control to OS native driver.
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**/
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int aer_osc_setup(struct pcie_device *pciedev)
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{
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acpi_status status = AE_NOT_FOUND;
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struct pci_dev *pdev = pciedev->port;
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acpi_handle handle = NULL;
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if (acpi_pci_disabled)
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return -1;
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handle = acpi_find_root_bridge_handle(pdev);
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if (handle) {
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status = acpi_pci_osc_control_set(handle,
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OSC_PCI_EXPRESS_AER_CONTROL |
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OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
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}
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if (ACPI_FAILURE(status)) {
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dev_printk(KERN_DEBUG, &pciedev->device, "AER service couldn't "
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"init device: %s\n",
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(status == AE_SUPPORT || status == AE_NOT_FOUND) ?
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"no _OSC support" : "_OSC failed");
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return -1;
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}
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return 0;
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}
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#ifdef CONFIG_ACPI_APEI
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static inline int hest_match_pci(struct acpi_hest_aer_common *p,
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struct pci_dev *pci)
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{
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return (0 == pci_domain_nr(pci->bus) &&
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p->bus == pci->bus->number &&
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p->device == PCI_SLOT(pci->devfn) &&
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p->function == PCI_FUNC(pci->devfn));
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}
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struct aer_hest_parse_info {
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struct pci_dev *pci_dev;
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int firmware_first;
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};
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static int aer_hest_parse(struct acpi_hest_header *hest_hdr, void *data)
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{
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struct aer_hest_parse_info *info = data;
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struct acpi_hest_aer_common *p;
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u8 pcie_type = 0;
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u8 bridge = 0;
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int ff = 0;
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switch (hest_hdr->type) {
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case ACPI_HEST_TYPE_AER_ROOT_PORT:
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pcie_type = PCI_EXP_TYPE_ROOT_PORT;
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break;
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case ACPI_HEST_TYPE_AER_ENDPOINT:
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pcie_type = PCI_EXP_TYPE_ENDPOINT;
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break;
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case ACPI_HEST_TYPE_AER_BRIDGE:
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if ((info->pci_dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
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bridge = 1;
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break;
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default:
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return 0;
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}
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p = (struct acpi_hest_aer_common *)(hest_hdr + 1);
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if (p->flags & ACPI_HEST_GLOBAL) {
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if ((info->pci_dev->is_pcie &&
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info->pci_dev->pcie_type == pcie_type) || bridge)
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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} else
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if (hest_match_pci(p, info->pci_dev))
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ff = !!(p->flags & ACPI_HEST_FIRMWARE_FIRST);
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info->firmware_first = ff;
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return 0;
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}
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static void aer_set_firmware_first(struct pci_dev *pci_dev)
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{
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int rc;
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struct aer_hest_parse_info info = {
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.pci_dev = pci_dev,
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.firmware_first = 0,
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};
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rc = apei_hest_parse(aer_hest_parse, &info);
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if (rc)
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pci_dev->__aer_firmware_first = 0;
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else
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pci_dev->__aer_firmware_first = info.firmware_first;
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pci_dev->__aer_firmware_first_valid = 1;
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}
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int pcie_aer_get_firmware_first(struct pci_dev *dev)
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{
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if (!dev->__aer_firmware_first_valid)
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aer_set_firmware_first(dev);
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return dev->__aer_firmware_first;
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}
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#endif
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