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Multi Format Codec 5.1 is a hardware video coding acceleration module found in the S5PV210 and Exynos4 Samsung SoCs. It is capable of handling a range of video codecs and this driver provides a V4L2 interface for video decoding and encoding. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Jeongtae Park <jtp.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
92 lines
3.4 KiB
C
92 lines
3.4 KiB
C
/*
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* drivers/media/video/samsung/mfc5/s5p_mfc_opr.h
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*
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* Header file for Samsung MFC (Multi Function Codec - FIMV) driver
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* Contains declarations of hw related functions.
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*
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* Kamil Debski, Copyright (C) 2011 Samsung Electronics
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef S5P_MFC_OPR_H_
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#define S5P_MFC_OPR_H_
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#include "s5p_mfc_common.h"
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int s5p_mfc_init_decode(struct s5p_mfc_ctx *ctx);
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int s5p_mfc_init_encode(struct s5p_mfc_ctx *mfc_ctx);
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/* Decoding functions */
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int s5p_mfc_set_dec_frame_buffer(struct s5p_mfc_ctx *ctx);
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int s5p_mfc_set_dec_stream_buffer(struct s5p_mfc_ctx *ctx, int buf_addr,
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unsigned int start_num_byte,
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unsigned int buf_size);
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/* Encoding functions */
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void s5p_mfc_set_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
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unsigned long y_addr, unsigned long c_addr);
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int s5p_mfc_set_enc_stream_buffer(struct s5p_mfc_ctx *ctx,
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unsigned long addr, unsigned int size);
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void s5p_mfc_get_enc_frame_buffer(struct s5p_mfc_ctx *ctx,
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unsigned long *y_addr, unsigned long *c_addr);
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int s5p_mfc_set_enc_ref_buffer(struct s5p_mfc_ctx *mfc_ctx);
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int s5p_mfc_decode_one_frame(struct s5p_mfc_ctx *ctx,
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enum s5p_mfc_decode_arg last_frame);
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int s5p_mfc_encode_one_frame(struct s5p_mfc_ctx *mfc_ctx);
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/* Memory allocation */
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int s5p_mfc_alloc_dec_temp_buffers(struct s5p_mfc_ctx *ctx);
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void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
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void s5p_mfc_release_dec_desc_buffer(struct s5p_mfc_ctx *ctx);
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int s5p_mfc_alloc_codec_buffers(struct s5p_mfc_ctx *ctx);
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void s5p_mfc_release_codec_buffers(struct s5p_mfc_ctx *ctx);
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int s5p_mfc_alloc_instance_buffer(struct s5p_mfc_ctx *ctx);
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void s5p_mfc_release_instance_buffer(struct s5p_mfc_ctx *ctx);
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void s5p_mfc_try_run(struct s5p_mfc_dev *dev);
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void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
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#define s5p_mfc_get_dspl_y_adr() (readl(dev->regs_base + \
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S5P_FIMV_SI_DISPLAY_Y_ADR) << \
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MFC_OFFSET_SHIFT)
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#define s5p_mfc_get_dec_y_adr() (readl(dev->regs_base + \
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S5P_FIMV_SI_DISPLAY_Y_ADR) << \
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MFC_OFFSET_SHIFT)
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#define s5p_mfc_get_dspl_status() readl(dev->regs_base + \
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S5P_FIMV_SI_DISPLAY_STATUS)
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#define s5p_mfc_get_frame_type() (readl(dev->regs_base + \
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S5P_FIMV_DECODE_FRAME_TYPE) \
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& S5P_FIMV_DECODE_FRAME_MASK)
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#define s5p_mfc_get_consumed_stream() readl(dev->regs_base + \
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S5P_FIMV_SI_CONSUMED_BYTES)
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#define s5p_mfc_get_int_reason() (readl(dev->regs_base + \
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S5P_FIMV_RISC2HOST_CMD) & \
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S5P_FIMV_RISC2HOST_CMD_MASK)
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#define s5p_mfc_get_int_err() readl(dev->regs_base + \
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S5P_FIMV_RISC2HOST_ARG2)
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#define s5p_mfc_err_dec(x) (((x) & S5P_FIMV_ERR_DEC_MASK) >> \
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S5P_FIMV_ERR_DEC_SHIFT)
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#define s5p_mfc_err_dspl(x) (((x) & S5P_FIMV_ERR_DSPL_MASK) >> \
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S5P_FIMV_ERR_DSPL_SHIFT)
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#define s5p_mfc_get_img_width() readl(dev->regs_base + \
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S5P_FIMV_SI_HRESOL)
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#define s5p_mfc_get_img_height() readl(dev->regs_base + \
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S5P_FIMV_SI_VRESOL)
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#define s5p_mfc_get_dpb_count() readl(dev->regs_base + \
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S5P_FIMV_SI_BUF_NUMBER)
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#define s5p_mfc_get_inst_no() readl(dev->regs_base + \
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S5P_FIMV_RISC2HOST_ARG1)
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#define s5p_mfc_get_enc_strm_size() readl(dev->regs_base + \
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S5P_FIMV_ENC_SI_STRM_SIZE)
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#define s5p_mfc_get_enc_slice_type() readl(dev->regs_base + \
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S5P_FIMV_ENC_SI_SLICE_TYPE)
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#endif /* S5P_MFC_OPR_H_ */
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