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0af8330525
The pcie-controller node needs to be relocated according the MBus DT binding, since it's now a child of the mbus-compatible node. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
110 lines
2.0 KiB
Plaintext
110 lines
2.0 KiB
Plaintext
/*
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* Device Tree file for Marvell Armada 370 Reference Design board
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* (RD-88F6710-A1)
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*
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* Copied from arch/arm/boot/dts/armada-370-db.dts
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*
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* Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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#include "armada-370.dtsi"
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/ {
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model = "Marvell Armada 370 Reference Design";
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compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; /* 512 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
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pcie-controller {
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status = "okay";
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/* Internal mini-PCIe connector */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Internal mini-PCIe connector */
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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clock-frequency = <200000000>;
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins1>;
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pinctrl-names = "default";
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status = "okay";
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/* No CD or WP GPIOs */
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broken-cd;
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};
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usb@50000 {
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status = "okay";
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};
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usb@51000 {
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status = "okay";
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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button@1 {
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label = "Software Button";
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linux,code = <116>;
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gpios = <&gpio0 6 1>;
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};
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};
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};
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};
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};
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