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This patch adds FCoE ( Fibre Channel Over Ethernet ) code for Intel XL710 adapters. This patch is limited to only new FCoE offloads code in newly added files by this patch and then following patches in the series modifies rest of the existing driver to enable FCoE with i40e driver. Signed-off-by: Vasu Dev <vasu.dev@intel.com> Tested-by: Jack Morgan<jack.morgan@intel.com> Signed-off-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
129 lines
4.1 KiB
C
129 lines
4.1 KiB
C
/*******************************************************************************
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*
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* Intel Ethernet Controller XL710 Family Linux Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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******************************************************************************/
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#ifndef _I40E_FCOE_H_
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#define _I40E_FCOE_H_
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/* FCoE HW context helper macros */
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#define I40E_DDP_CONTEXT_DESC(R, i) \
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(&(((struct i40e_fcoe_ddp_context_desc *)((R)->desc))[i]))
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#define I40E_QUEUE_CONTEXT_DESC(R, i) \
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(&(((struct i40e_fcoe_queue_context_desc *)((R)->desc))[i]))
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#define I40E_FILTER_CONTEXT_DESC(R, i) \
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(&(((struct i40e_fcoe_filter_context_desc *)((R)->desc))[i]))
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/* receive queue descriptor filter status for FCoE */
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#define I40E_RX_DESC_FLTSTAT_FCMASK 0x3
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#define I40E_RX_DESC_FLTSTAT_NOMTCH 0x0 /* no ddp context match */
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#define I40E_RX_DESC_FLTSTAT_NODDP 0x1 /* no ddp due to error */
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#define I40E_RX_DESC_FLTSTAT_DDP 0x2 /* DDPed payload, post header */
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#define I40E_RX_DESC_FLTSTAT_FCPRSP 0x3 /* FCP_RSP */
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/* receive queue descriptor error codes for FCoE */
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#define I40E_RX_DESC_FCOE_ERROR_MASK \
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(I40E_RX_DESC_ERROR_L3L4E_PROT | \
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I40E_RX_DESC_ERROR_L3L4E_FC | \
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I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR | \
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I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN)
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/* receive queue descriptor programming error */
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#define I40E_RX_PROG_FCOE_ERROR_TBL_FULL(e) \
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(((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT) & 0x1)
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#define I40E_RX_PROG_FCOE_ERROR_CONFLICT(e) \
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(((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT) & 0x1)
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#define I40E_RX_PROG_FCOE_ERROR_TBL_FULL_BIT \
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(1 << I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT)
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#define I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT \
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(1 << I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT)
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#define I40E_RX_PROG_FCOE_ERROR_INVLFAIL(e) \
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I40E_RX_PROG_FCOE_ERROR_CONFLICT(e)
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#define I40E_RX_PROG_FCOE_ERROR_INVLFAIL_BIT \
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I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT
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/* FCoE DDP related definitions */
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#define I40E_FCOE_MIN_XID 0x0000 /* the min xid supported by fcoe_sw */
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#define I40E_FCOE_MAX_XID 0x0FFF /* the max xid supported by fcoe_sw */
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#define I40E_FCOE_DDP_BUFFCNT_MAX 512 /* 9 bits bufcnt */
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#define I40E_FCOE_DDP_PTR_ALIGN 16
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#define I40E_FCOE_DDP_PTR_MAX (I40E_FCOE_DDP_BUFFCNT_MAX * sizeof(dma_addr_t))
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#define I40E_FCOE_DDP_BUF_MIN 4096
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#define I40E_FCOE_DDP_MAX 2048
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#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
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/* supported netdev features for FCoE */
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#define I40E_FCOE_NETIF_FEATURES (NETIF_F_ALL_FCOE | \
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NETIF_F_HW_VLAN_CTAG_TX | \
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NETIF_F_HW_VLAN_CTAG_RX | \
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NETIF_F_HW_VLAN_CTAG_FILTER)
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/* DDP context flags */
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enum i40e_fcoe_ddp_flags {
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__I40E_FCOE_DDP_NONE = 1,
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__I40E_FCOE_DDP_TARGET,
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__I40E_FCOE_DDP_INITALIZED,
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__I40E_FCOE_DDP_PROGRAMMED,
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__I40E_FCOE_DDP_DONE,
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__I40E_FCOE_DDP_ABORTED,
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__I40E_FCOE_DDP_UNMAPPED,
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};
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/* DDP SW context struct */
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struct i40e_fcoe_ddp {
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int len;
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u16 xid;
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u16 firstoff;
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u16 lastsize;
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u16 list_len;
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u8 fcerr;
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u8 prerr;
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unsigned long flags;
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unsigned int sgc;
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struct scatterlist *sgl;
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dma_addr_t udp;
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u64 *udl;
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struct dma_pool *pool;
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};
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struct i40e_fcoe_ddp_pool {
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struct dma_pool *pool;
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};
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struct i40e_fcoe {
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unsigned long mode;
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atomic_t refcnt;
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struct i40e_fcoe_ddp_pool __percpu *ddp_pool;
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struct i40e_fcoe_ddp ddp[I40E_FCOE_DDP_MAX];
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};
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#endif /* _I40E_FCOE_H_ */
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