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7a22323b23
The PXA3xx does not support the use of interrupts during reset and access to the GPIO status requires similar handling to that for PXA27x. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
485 lines
12 KiB
C
485 lines
12 KiB
C
/*
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* linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
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*
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* Author: Nicolas Pitre
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* Created: Dec 02, 2004
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/irq.h>
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#include <linux/mutex.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa2xx-gpio.h>
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#include <asm/arch/audio.h>
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#include "pxa2xx-pcm.h"
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#include "pxa2xx-ac97.h"
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static DEFINE_MUTEX(car_mutex);
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static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static volatile long gsr_bits;
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static struct clk *ac97_clk;
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#ifdef CONFIG_PXA27x
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static struct clk *ac97conf_clk;
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#endif
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/*
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* Beware PXA27x bugs:
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*
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* o Slot 12 read from modem space will hang controller.
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* o CDONE, SDONE interrupt fails after any slot 12 IO.
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*
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* We therefore have an hybrid approach for waiting on SDONE (interrupt or
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* 1 jiffy timeout if interrupt never comes).
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*/
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static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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unsigned short val = -1;
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volatile u32 *reg_addr;
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec/modem space */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
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else
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#endif
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reg_addr += (reg >> 1);
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#ifndef CONFIG_PXA27x
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if (reg == AC97_GPIO_STATUS) {
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/* read from controller cache */
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val = *reg_addr;
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goto out;
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}
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#endif
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/* start read access across the ac97 link */
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GSR = GSR_CDONE | GSR_SDONE;
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gsr_bits = 0;
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val = *reg_addr;
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wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
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if (!((GSR | gsr_bits) & GSR_SDONE)) {
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printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n",
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__func__, reg, GSR | gsr_bits);
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val = -1;
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goto out;
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}
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/* valid data now */
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GSR = GSR_CDONE | GSR_SDONE;
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gsr_bits = 0;
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val = *reg_addr;
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/* but we've just started another cycle... */
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wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
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out: mutex_unlock(&car_mutex);
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return val;
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}
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static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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volatile u32 *reg_addr;
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec/modem space */
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#else
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if (reg == AC97_GPIO_STATUS)
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reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
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else
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reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
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#endif
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reg_addr += (reg >> 1);
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GSR = GSR_CDONE | GSR_SDONE;
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gsr_bits = 0;
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*reg_addr = val;
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wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1);
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if (!((GSR | gsr_bits) & GSR_CDONE))
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printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n",
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__func__, reg, GSR | gsr_bits);
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mutex_unlock(&car_mutex);
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}
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static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 100;
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#endif
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gsr_bits = 0;
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#ifdef CONFIG_PXA27x
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/* warm reset broken on Bulverde,
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so manually keep AC97 reset high */
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pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
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udelay(10);
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GCR |= GCR_WARM_RST;
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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udelay(500);
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#elif defined(CONFIG_PXA3xx)
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/* Can't use interrupts */
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GCR |= GCR_WARM_RST;
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while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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#else
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GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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#endif
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if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
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printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
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__func__, gsr_bits);
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
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}
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static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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#ifdef CONFIG_PXA3xx
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int timeout = 1000;
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/* Hold CLKBPB for 100us */
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GCR = 0;
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GCR = GCR_CLKBPB;
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udelay(100);
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GCR = 0;
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#endif
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GCR &= GCR_COLD_RST; /* clear everything but nCRST */
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GCR &= ~GCR_COLD_RST; /* then assert nCRST */
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gsr_bits = 0;
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#ifdef CONFIG_PXA27x
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/* PXA27x Developers Manual section 13.5.2.2.1 */
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clk_enable(ac97conf_clk);
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udelay(5);
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clk_disable(ac97conf_clk);
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GCR = GCR_COLD_RST;
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udelay(50);
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#elif defined(CONFIG_PXA3xx)
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/* Can't use interrupts on PXA3xx */
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR = GCR_WARM_RST | GCR_COLD_RST;
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while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(10);
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#else
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GCR = GCR_COLD_RST;
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GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
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wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
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#endif
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if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
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printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
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__func__, gsr_bits);
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GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
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}
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static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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{
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long status;
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status = GSR;
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if (status) {
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GSR = status;
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gsr_bits |= status;
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wake_up(&gsr_wq);
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#ifdef CONFIG_PXA27x
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/* Although we don't use those we still need to clear them
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since they tend to spuriously trigger when MMC is used
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(hardware bug? go figure)... */
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MISR = MISR_EOC;
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PISR = PISR_EOC;
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MCSR = MCSR_EOC;
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#endif
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = pxa2xx_ac97_read,
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.write = pxa2xx_ac97_write,
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.warm_reset = pxa2xx_ac97_warm_reset,
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.reset = pxa2xx_ac97_cold_reset,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
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.name = "AC97 PCM Stereo out",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRTXPCDR,
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
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.name = "AC97 PCM Stereo in",
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.dev_addr = __PREG(PCDR),
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.drcmr = &DRCMRRXPCDR,
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST32 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
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.name = "AC97 Aux PCM (Slot 5) Mono out",
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.dev_addr = __PREG(MODR),
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.drcmr = &DRCMRTXMODR,
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
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.name = "AC97 Aux PCM (Slot 5) Mono in",
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.dev_addr = __PREG(MODR),
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.drcmr = &DRCMRRXMODR,
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
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.name = "AC97 Mic PCM (Slot 6) Mono in",
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.dev_addr = __PREG(MCDR),
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.drcmr = &DRCMRRXMCDR,
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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#ifdef CONFIG_PM
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static int pxa2xx_ac97_suspend(struct platform_device *pdev,
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struct snd_soc_cpu_dai *dai)
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{
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GCR |= GCR_ACLINK_OFF;
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clk_disable(ac97_clk);
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return 0;
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}
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static int pxa2xx_ac97_resume(struct platform_device *pdev,
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struct snd_soc_cpu_dai *dai)
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{
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pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
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pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
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pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
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pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
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#ifdef CONFIG_PXA27x
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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#endif
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clk_enable(ac97_clk);
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return 0;
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}
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#else
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#define pxa2xx_ac97_suspend NULL
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#define pxa2xx_ac97_resume NULL
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#endif
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static int pxa2xx_ac97_probe(struct platform_device *pdev)
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{
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int ret;
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ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
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if (ret < 0)
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goto err;
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pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
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pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
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pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
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pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
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#ifdef CONFIG_PXA27x
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
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ac97conf_clk = clk_get(&pdev->dev, "AC97CONFCLK");
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if (IS_ERR(ac97conf_clk)) {
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ret = PTR_ERR(ac97conf_clk);
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ac97conf_clk = NULL;
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goto err_irq;
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}
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#endif
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ac97_clk = clk_get(&pdev->dev, "AC97CLK");
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if (IS_ERR(ac97_clk)) {
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ret = PTR_ERR(ac97_clk);
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ac97_clk = NULL;
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goto err_irq;
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}
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clk_enable(ac97_clk);
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return 0;
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err_irq:
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GCR |= GCR_ACLINK_OFF;
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#ifdef CONFIG_PXA27x
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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}
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#endif
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free_irq(IRQ_AC97, NULL);
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err:
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return ret;
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}
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static void pxa2xx_ac97_remove(struct platform_device *pdev)
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{
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GCR |= GCR_ACLINK_OFF;
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free_irq(IRQ_AC97, NULL);
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#ifdef CONFIG_PXA27x
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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#endif
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clk_disable(ac97_clk);
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clk_put(ac97_clk);
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ac97_clk = NULL;
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}
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static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out;
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else
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cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in;
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return 0;
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}
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static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
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else
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cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
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return 0;
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}
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static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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return -ENODEV;
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else
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cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in;
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return 0;
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}
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#define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
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SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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/*
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* There is only 1 physical AC97 interface for pxa2xx, but it
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* has extra fifo's that can be used for aux DACs and ADCs.
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*/
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struct snd_soc_cpu_dai pxa_ac97_dai[] = {
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{
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.name = "pxa2xx-ac97",
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.id = 0,
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.type = SND_SOC_DAI_AC97,
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.probe = pxa2xx_ac97_probe,
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.remove = pxa2xx_ac97_remove,
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.suspend = pxa2xx_ac97_suspend,
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.resume = pxa2xx_ac97_resume,
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.playback = {
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.stream_name = "AC97 Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = PXA2XX_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.capture = {
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.stream_name = "AC97 Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = PXA2XX_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = {
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.hw_params = pxa2xx_ac97_hw_params,},
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},
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{
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.name = "pxa2xx-ac97-aux",
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.id = 1,
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.type = SND_SOC_DAI_AC97,
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.playback = {
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.stream_name = "AC97 Aux Playback",
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.channels_min = 1,
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.channels_max = 1,
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.rates = PXA2XX_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.capture = {
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.stream_name = "AC97 Aux Capture",
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.channels_min = 1,
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.channels_max = 1,
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.rates = PXA2XX_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = {
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.hw_params = pxa2xx_ac97_hw_aux_params,},
|
|
},
|
|
{
|
|
.name = "pxa2xx-ac97-mic",
|
|
.id = 2,
|
|
.type = SND_SOC_DAI_AC97,
|
|
.capture = {
|
|
.stream_name = "AC97 Mic Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 1,
|
|
.rates = PXA2XX_AC97_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,},
|
|
.ops = {
|
|
.hw_params = pxa2xx_ac97_hw_mic_params,},
|
|
},
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(pxa_ac97_dai);
|
|
EXPORT_SYMBOL_GPL(soc_ac97_ops);
|
|
|
|
MODULE_AUTHOR("Nicolas Pitre");
|
|
MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
|
|
MODULE_LICENSE("GPL");
|