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dc4910d9e9
When pci_base is accessed whereas it has not been properly mapped by of_iomap() the kernel hang. The check of this pointer made an improper use of IS_ERR() instead of comparing to NULL. This patch fix this issue. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Cc: stable@vger.kernel.org # v3.12+:af8d1c63af: ARM: mvebu: Add support to get the ID and the revision of a SoC Cc: stable@vger.kernel.org # v3.12+:85e618a1be: ARM: mvebu: Add quirk for i2c for the OpenBlocks AX3-4 board Cc: stable@vger.kernel.org # v3.12+:6cf70ae928: i2c: mv64xxx: Fix bus hang on A0 version of the Armada XP SoCs Cc: stable@vger.kernel.org # v3.12+:f8b94beb7e: i2c: mv64xxx: Document the newly introduced Armada XP A0 compatible Cc: stable@vger.kernel.org # v3.12+ Fixes:930ab3d403(i2c: mv64xxx: Add I2C Transaction Generator support) Signed-off-by: Jason Cooper <jason@lakedaemon.net>
120 lines
2.5 KiB
C
120 lines
2.5 KiB
C
/*
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* ID and revision information for mvebu SoCs
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* All the mvebu SoCs have information related to their variant and
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* revision that can be read from the PCI control register. This is
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* done before the PCI initialization to avoid any conflict. Once the
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* ID and revision are retrieved, the mapping is freed.
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*/
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#define pr_fmt(fmt) "mvebu-soc-id: " fmt
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "mvebu-soc-id.h"
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#define PCIE_DEV_ID_OFF 0x0
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#define PCIE_DEV_REV_OFF 0x8
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#define SOC_ID_MASK 0xFFFF0000
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#define SOC_REV_MASK 0xFF
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static u32 soc_dev_id;
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static u32 soc_rev;
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static bool is_id_valid;
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static const struct of_device_id mvebu_pcie_of_match_table[] = {
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{ .compatible = "marvell,armada-xp-pcie", },
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{ .compatible = "marvell,armada-370-pcie", },
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{},
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};
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int mvebu_get_soc_id(u32 *dev, u32 *rev)
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{
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if (is_id_valid) {
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*dev = soc_dev_id;
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*rev = soc_rev;
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return 0;
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} else
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return -1;
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}
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static int __init mvebu_soc_id_init(void)
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{
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struct device_node *np;
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int ret = 0;
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void __iomem *pci_base;
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struct clk *clk;
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struct device_node *child;
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np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
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if (!np)
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return ret;
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/*
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* ID and revision are available from any port, so we
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* just pick the first one
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*/
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child = of_get_next_child(np, NULL);
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if (child == NULL) {
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pr_err("cannot get pci node\n");
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ret = -ENOMEM;
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goto clk_err;
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}
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clk = of_clk_get_by_name(child, NULL);
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if (IS_ERR(clk)) {
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pr_err("cannot get clock\n");
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ret = -ENOMEM;
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goto clk_err;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("cannot enable clock\n");
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goto clk_err;
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}
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pci_base = of_iomap(child, 0);
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if (pci_base == NULL) {
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pr_err("cannot map registers\n");
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ret = -ENOMEM;
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goto res_ioremap;
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}
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/* SoC ID */
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soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
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/* SoC revision */
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soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
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is_id_valid = true;
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pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
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iounmap(pci_base);
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res_ioremap:
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clk_disable_unprepare(clk);
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clk_err:
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of_node_put(child);
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of_node_put(np);
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return ret;
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}
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core_initcall(mvebu_soc_id_init);
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