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2f0a81a245
Use the new PM macros for the suspend and resume functions to be automatically dropped by the compiler when CONFIG_PM or CONFIG_PM_SLEEP are disabled, without having to use #ifdef guards. This has the advantage of always compiling these functions in, independently of any Kconfig option. Thanks to that, bugs and other regressions are subsequently easier to catch. Note that the behaviour is slightly different than before; the original code wrapped the suspend/resume with #ifdef CONFIG_PM guards, which resulted in these functions being compiled in but never used when CONFIG_PM_SLEEP was disabled. Now, those functions are only compiled in when CONFIG_PM_SLEEP is enabled. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20230722115046.27323-2-paul@crapouillou.net Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
381 lines
8.3 KiB
C
381 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
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* Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
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*
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* 2.6 port by Matt Porter <mporter@kernel.crashing.org>
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*
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* The documentation describes this as an SMBus controller, but it doesn't
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* understand any of the SMBus protocol in hardware. It's really an I2C
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* controller that could emulate most of the SMBus in software.
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*
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* This is just a skeleton adapter to use with the Au1550 PSC
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* algorithm. It was developed for the Pb1550, but will work with
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* any Au1550 board that has a similar PSC configuration.
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#define PSC_SEL 0x00
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#define PSC_CTRL 0x04
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#define PSC_SMBCFG 0x08
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#define PSC_SMBMSK 0x0C
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#define PSC_SMBPCR 0x10
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#define PSC_SMBSTAT 0x14
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#define PSC_SMBEVNT 0x18
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#define PSC_SMBTXRX 0x1C
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#define PSC_SMBTMR 0x20
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struct i2c_au1550_data {
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void __iomem *psc_base;
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int xfer_timeout;
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struct i2c_adapter adap;
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};
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static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v)
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{
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__raw_writel(v, a->psc_base + r);
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wmb();
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}
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static inline unsigned long RD(struct i2c_au1550_data *a, int r)
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{
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return __raw_readl(a->psc_base + r);
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}
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static int wait_xfer_done(struct i2c_au1550_data *adap)
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{
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int i;
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/* Wait for Tx Buffer Empty */
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for (i = 0; i < adap->xfer_timeout; i++) {
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if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int wait_ack(struct i2c_au1550_data *adap)
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{
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unsigned long stat;
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if (wait_xfer_done(adap))
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return -ETIMEDOUT;
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stat = RD(adap, PSC_SMBEVNT);
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if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
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return -ETIMEDOUT;
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return 0;
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}
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static int wait_master_done(struct i2c_au1550_data *adap)
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{
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int i;
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/* Wait for Master Done. */
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for (i = 0; i < 2 * adap->xfer_timeout; i++) {
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if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0)
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int
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do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q)
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{
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unsigned long stat;
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/* Reset the FIFOs, clear events. */
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stat = RD(adap, PSC_SMBSTAT);
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WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR);
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if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) {
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WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC);
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while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0)
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cpu_relax();
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udelay(50);
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}
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/* Write out the i2c chip address and specify operation */
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addr <<= 1;
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if (rd)
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addr |= 1;
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/* zero-byte xfers stop immediately */
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if (q)
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addr |= PSC_SMBTXRX_STP;
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/* Put byte into fifo, start up master. */
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WR(adap, PSC_SMBTXRX, addr);
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WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS);
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if (wait_ack(adap))
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return -EIO;
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return (q) ? wait_master_done(adap) : 0;
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}
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static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out)
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{
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int j;
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if (wait_xfer_done(adap))
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return -EIO;
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j = adap->xfer_timeout * 100;
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do {
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j--;
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if (j <= 0)
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return -EIO;
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if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0)
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j = 0;
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else
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udelay(1);
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} while (j > 0);
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*out = RD(adap, PSC_SMBTXRX);
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return 0;
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}
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static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
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unsigned int len)
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{
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int i;
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if (len == 0)
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return 0;
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/* A read is performed by stuffing the transmit fifo with
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* zero bytes for timing, waiting for bytes to appear in the
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* receive fifo, then reading the bytes.
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*/
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i = 0;
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while (i < (len - 1)) {
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WR(adap, PSC_SMBTXRX, 0);
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if (wait_for_rx_byte(adap, &buf[i]))
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return -EIO;
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i++;
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}
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/* The last byte has to indicate transfer done. */
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WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP);
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if (wait_master_done(adap))
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return -EIO;
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buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff);
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return 0;
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}
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static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
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unsigned int len)
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{
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int i;
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unsigned long data;
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if (len == 0)
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return 0;
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i = 0;
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while (i < (len-1)) {
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data = buf[i];
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WR(adap, PSC_SMBTXRX, data);
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if (wait_ack(adap))
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return -EIO;
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i++;
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}
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/* The last byte has to indicate transfer done. */
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data = buf[i];
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data |= PSC_SMBTXRX_STP;
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WR(adap, PSC_SMBTXRX, data);
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if (wait_master_done(adap))
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return -EIO;
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return 0;
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}
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static int
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au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
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{
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struct i2c_au1550_data *adap = i2c_adap->algo_data;
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struct i2c_msg *p;
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int i, err = 0;
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WR(adap, PSC_CTRL, PSC_CTRL_ENABLE);
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for (i = 0; !err && i < num; i++) {
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p = &msgs[i];
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err = do_address(adap, p->addr, p->flags & I2C_M_RD,
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(p->len == 0));
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if (err || !p->len)
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continue;
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if (p->flags & I2C_M_RD)
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err = i2c_read(adap, p->buf, p->len);
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else
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err = i2c_write(adap, p->buf, p->len);
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}
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/* Return the number of messages processed, or the error code.
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*/
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if (err == 0)
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err = num;
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WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND);
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return err;
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}
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static u32 au1550_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm au1550_algo = {
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.master_xfer = au1550_xfer,
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.functionality = au1550_func,
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};
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static void i2c_au1550_setup(struct i2c_au1550_data *priv)
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{
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unsigned long cfg;
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WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
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WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE);
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WR(priv, PSC_SMBCFG, 0);
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WR(priv, PSC_CTRL, PSC_CTRL_ENABLE);
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while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
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cpu_relax();
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cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE;
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WR(priv, PSC_SMBCFG, cfg);
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/* Divide by 8 to get a 6.25 MHz clock. The later protocol
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* timings are based on this clock.
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*/
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cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
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WR(priv, PSC_SMBCFG, cfg);
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WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK);
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/* Set the protocol timer values. See Table 71 in the
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* Au1550 Data Book for standard timing values.
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*/
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WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(20) | \
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PSC_SMBTMR_SET_PU(20) | PSC_SMBTMR_SET_SH(20) | \
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PSC_SMBTMR_SET_SU(20) | PSC_SMBTMR_SET_CL(20) | \
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PSC_SMBTMR_SET_CH(20));
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cfg |= PSC_SMBCFG_DE_ENABLE;
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WR(priv, PSC_SMBCFG, cfg);
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while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0)
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cpu_relax();
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WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND);
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}
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static void i2c_au1550_disable(struct i2c_au1550_data *priv)
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{
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WR(priv, PSC_SMBCFG, 0);
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WR(priv, PSC_CTRL, PSC_CTRL_DISABLE);
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}
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/*
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* registering functions to load algorithms at runtime
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* Prior to calling us, the 50MHz clock frequency and routing
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* must have been set up for the PSC indicated by the adapter.
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*/
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static int
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i2c_au1550_probe(struct platform_device *pdev)
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{
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struct i2c_au1550_data *priv;
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int ret;
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priv = devm_kzalloc(&pdev->dev, sizeof(struct i2c_au1550_data),
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GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->psc_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(priv->psc_base))
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return PTR_ERR(priv->psc_base);
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priv->xfer_timeout = 200;
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priv->adap.nr = pdev->id;
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priv->adap.algo = &au1550_algo;
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priv->adap.algo_data = priv;
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priv->adap.dev.parent = &pdev->dev;
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strscpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name));
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/* Now, set up the PSC for SMBus PIO mode. */
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i2c_au1550_setup(priv);
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ret = i2c_add_numbered_adapter(&priv->adap);
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if (ret) {
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i2c_au1550_disable(priv);
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return ret;
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}
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static void i2c_au1550_remove(struct platform_device *pdev)
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{
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struct i2c_au1550_data *priv = platform_get_drvdata(pdev);
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i2c_del_adapter(&priv->adap);
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i2c_au1550_disable(priv);
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}
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static int i2c_au1550_suspend(struct device *dev)
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{
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struct i2c_au1550_data *priv = dev_get_drvdata(dev);
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i2c_au1550_disable(priv);
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return 0;
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}
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static int i2c_au1550_resume(struct device *dev)
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{
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struct i2c_au1550_data *priv = dev_get_drvdata(dev);
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i2c_au1550_setup(priv);
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(i2c_au1550_pmops,
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i2c_au1550_suspend, i2c_au1550_resume);
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static struct platform_driver au1xpsc_smbus_driver = {
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.driver = {
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.name = "au1xpsc_smbus",
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.pm = pm_sleep_ptr(&i2c_au1550_pmops),
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},
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.probe = i2c_au1550_probe,
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.remove_new = i2c_au1550_remove,
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};
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module_platform_driver(au1xpsc_smbus_driver);
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MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
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MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:au1xpsc_smbus");
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