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882407b979
Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
170 lines
3.7 KiB
C
170 lines
3.7 KiB
C
/*
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* Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
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*
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* Description:
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* MPC832xE MDS board specific routines.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/initrd.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ipic.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/qe.h>
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#include <asm/qe_ic.h>
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#include "mpc83xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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static u8 *bcsr_regs = NULL;
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/* ************************************************************************
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*
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* Setup the architecture
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*
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*/
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static void __init mpc832x_sys_setup_arch(void)
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{
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struct device_node *np;
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if (ppc_md.progress)
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ppc_md.progress("mpc832x_sys_setup_arch()", 0);
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/* Map BCSR area */
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np = of_find_node_by_name(NULL, "bcsr");
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if (np != 0) {
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struct resource res;
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of_address_to_resource(np, 0, &res);
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bcsr_regs = ioremap(res.start, res.end - res.start +1);
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of_node_put(np);
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}
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
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mpc83xx_add_bridge(np);
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#endif
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#ifdef CONFIG_QUICC_ENGINE
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qe_reset();
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if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
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par_io_init(np);
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of_node_put(np);
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for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
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par_io_of_config(np);
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}
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if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
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!= NULL){
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/* Reset the Ethernet PHYs */
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#define BCSR8_FETH_RST 0x50
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bcsr_regs[8] &= ~BCSR8_FETH_RST;
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udelay(1000);
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bcsr_regs[8] |= BCSR8_FETH_RST;
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iounmap(bcsr_regs);
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of_node_put(np);
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}
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#endif /* CONFIG_QUICC_ENGINE */
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}
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static struct of_device_id mpc832x_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .type = "qe", },
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{},
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};
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static int __init mpc832x_declare_of_platform_devices(void)
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{
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if (!machine_is(mpc832x_mds))
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return 0;
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, mpc832x_ids, NULL);
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return 0;
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}
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device_initcall(mpc832x_declare_of_platform_devices);
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static void __init mpc832x_sys_init_IRQ(void)
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{
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struct device_node *np;
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np = of_find_node_by_type(NULL, "ipic");
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if (!np)
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return;
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ipic_init(np, 0);
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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ipic_set_default_priority();
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of_node_put(np);
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#ifdef CONFIG_QUICC_ENGINE
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np = of_find_node_by_type(NULL, "qeic");
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if (!np)
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return;
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qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
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of_node_put(np);
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#endif /* CONFIG_QUICC_ENGINE */
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}
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/*
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* Called very early, MMU is off, device-tree isn't unflattened
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*/
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static int __init mpc832x_sys_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "MPC832xMDS");
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}
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define_machine(mpc832x_mds) {
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.name = "MPC832x MDS",
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.probe = mpc832x_sys_probe,
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.setup_arch = mpc832x_sys_setup_arch,
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.init_IRQ = mpc832x_sys_init_IRQ,
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.get_irq = ipic_get_irq,
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.restart = mpc83xx_restart,
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.time_init = mpc83xx_time_init,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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