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The C6X SoCs contain several PLL controllers each with up to 16 clock outputs feeding into the cores or peripheral clock domains. The hardware is very similar to arm/mach-davinci clocks. This is still a work in progress which needs to be updated once device tree clock binding changes shake out. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
23 lines
329 B
C
23 lines
329 B
C
#ifndef _ASM_CLKDEV_H
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#define _ASM_CLKDEV_H
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#include <linux/slab.h>
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struct clk;
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static inline int __clk_get(struct clk *clk)
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{
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return 1;
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}
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static inline void __clk_put(struct clk *clk)
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{
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}
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static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
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{
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return kzalloc(size, GFP_KERNEL);
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}
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#endif /* _ASM_CLKDEV_H */
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