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86c679a522
This removes the conversion from pdiv to hw, which is already taken care of by _get_table_rate before this code is run. This avoids incorrectly converting pdiv to hw twice and getting the wrong hw value. Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while setting all the other fields. In order to prevent regressions on earlier SoC generations, all of the frequency tables need to be updated so that they contain the actual divider values. If they contain hardware values these would be converted to hardware values again, yielding the wrong value. Signed-off-by: Rhyland Klein <rklein@nvidia.com> [treding@nvidia.com: fix regressions on earlier SoC generations] Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| .. | ||
| clk-audio-sync.c | ||
| clk-dfll.c | ||
| clk-dfll.h | ||
| clk-divider.c | ||
| clk-emc.c | ||
| clk-id.h | ||
| clk-periph-gate.c | ||
| clk-periph.c | ||
| clk-pll-out.c | ||
| clk-pll.c | ||
| clk-super.c | ||
| clk-tegra20.c | ||
| clk-tegra30.c | ||
| clk-tegra114.c | ||
| clk-tegra124-dfll-fcpu.c | ||
| clk-tegra124.c | ||
| clk-tegra-audio.c | ||
| clk-tegra-fixed.c | ||
| clk-tegra-periph.c | ||
| clk-tegra-pmc.c | ||
| clk-tegra-super-gen4.c | ||
| clk.c | ||
| clk.h | ||
| cvb.c | ||
| cvb.h | ||
| Kconfig | ||
| Makefile | ||