linux/arch/mips/include/asm/pm-cps.h
Paul Burton fb615d61b5 Update MIPS email addresses
MIPS will soon not be a part of Imagination Technologies, and as such
many @imgtec.com email addresses will no longer be valid. This patch
updates the addresses for those who:

 - Have 10 or more patches in mainline authored using an @imgtec.com
   email address, or any patches dated within the past year.

 - Are still with Imagination but leaving as part of the MIPS business
   unit, as determined from an internal email address list.

 - Haven't already updated their email address (ie. JamesH) or expressed
   a desire to be excluded (ie. Maciej).

 - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt &
   myself.

New addresses are of the form firstname.lastname@mips.com, and all
verified against an internal email address list.  An entry is added to
.mailmap for each person such that get_maintainer.pl will report the new
addresses rather than @imgtec.com addresses which will soon be dead.

Instances of the affected addresses throughout the tree are then
mechanically replaced with the new @mips.com address.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com>
Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com>
Cc: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: Matt Redfearn <matt.redfearn@mips.com>
Acked-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-11-03 09:02:30 -07:00

54 lines
1.7 KiB
C

/*
* Copyright (C) 2014 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MIPS_ASM_PM_CPS_H__
#define __MIPS_ASM_PM_CPS_H__
/*
* The CM & CPC can only handle coherence & power control on a per-core basis,
* thus in an MT system the VP(E)s within each core are coupled and can only
* enter or exit states requiring CM or CPC assistance in unison.
*/
#if defined(CONFIG_CPU_MIPSR6)
# define coupled_coherence cpu_has_vp
#elif defined(CONFIG_MIPS_MT)
# define coupled_coherence cpu_has_mipsmt
#else
# define coupled_coherence 0
#endif
/* Enumeration of possible PM states */
enum cps_pm_state {
CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
CPS_PM_CLOCK_GATED, /* Core clock gated */
CPS_PM_POWER_GATED, /* Core power gated */
CPS_PM_STATE_COUNT,
};
/**
* cps_pm_support_state - determine whether the system supports a PM state
* @state: the state to test for support
*
* Returns true if the system supports the given state, otherwise false.
*/
extern bool cps_pm_support_state(enum cps_pm_state state);
/**
* cps_pm_enter_state - enter a PM state
* @state: the state to enter
*
* Enter the given PM state. If coupled_coherence is non-zero then it is
* expected that this function be called at approximately the same time on
* each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
*/
extern int cps_pm_enter_state(enum cps_pm_state state);
#endif /* __MIPS_ASM_PM_CPS_H__ */