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The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
64 lines
1.8 KiB
C
64 lines
1.8 KiB
C
/*
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* arch/arm/mach-tegra/reset.h
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*
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* CPU reset dispatcher.
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*
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* Copyright (c) 2011, NVIDIA Corporation.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_TEGRA_RESET_H
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#define __MACH_TEGRA_RESET_H
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#define TEGRA_RESET_MASK_PRESENT 0
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#define TEGRA_RESET_MASK_LP1 1
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#define TEGRA_RESET_MASK_LP2 2
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#define TEGRA_RESET_STARTUP_SECONDARY 3
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#define TEGRA_RESET_STARTUP_LP2 4
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#define TEGRA_RESET_STARTUP_LP1 5
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#define TEGRA_RESET_DATA_SIZE 6
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#ifndef __ASSEMBLY__
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#include "irammap.h"
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extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
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void __tegra_cpu_reset_handler_start(void);
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void __tegra_cpu_reset_handler(void);
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void __tegra_cpu_reset_handler_end(void);
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void tegra_secondary_startup(void);
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#ifdef CONFIG_PM_SLEEP
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#define tegra_cpu_lp1_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#define tegra_cpu_lp2_mask \
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(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
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((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
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(u32)__tegra_cpu_reset_handler_start)))
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#endif
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#define tegra_cpu_reset_handler_offset \
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((u32)__tegra_cpu_reset_handler - \
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(u32)__tegra_cpu_reset_handler_start)
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#define tegra_cpu_reset_handler_size \
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(__tegra_cpu_reset_handler_end - \
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__tegra_cpu_reset_handler_start)
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void __init tegra_cpu_reset_handler_init(void);
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#endif
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#endif
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