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The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
24 lines
732 B
Plaintext
24 lines
732 B
Plaintext
NVIDIA Tegra30 timer
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
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running counter, and 5 watchdog modules. The first two channels may also
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trigger a legacy watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 6 interrupts; one per each of timer channels 1
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through 5, and one for the shared interrupt for the remaining channels.
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timer {
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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};
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