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144 lines
7.5 KiB
C
144 lines
7.5 KiB
C
#ifndef __ASM_ARCH_REGS_UART_H
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#define __ASM_ARCH_REGS_UART_H
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/*
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* UARTs
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*/
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/* Full Function UART (FFUART) */
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#define FFUART FFRBR
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#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
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#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
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#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
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#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
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#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
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#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
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#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
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#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
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#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
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#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
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#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
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#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Bluetooth UART (BTUART) */
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#define BTUART BTRBR
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#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
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#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
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#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
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#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
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#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
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#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
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#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
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#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
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#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
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#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
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#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
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#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Standard UART (STUART) */
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#define STUART STRBR
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#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
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#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
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#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
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#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
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#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
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#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
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#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
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#define STLSR __REG(0x40700014) /* Line Status Register (read only) */
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#define STMSR __REG(0x40700018) /* Reserved */
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#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
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#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
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#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Hardware UART (HWUART) */
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#define HWUART HWRBR
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#define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
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#define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
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#define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
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#define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
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#define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
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#define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
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#define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
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#define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
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#define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
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#define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
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#define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
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#define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
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#define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
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#define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
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#define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
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#define IER_DMAE (1 << 7) /* DMA Requests Enable */
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#define IER_UUE (1 << 6) /* UART Unit Enable */
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#define IER_NRZE (1 << 5) /* NRZ coding Enable */
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#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
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#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
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#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
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#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
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#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
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#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
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#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
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#define IIR_TOD (1 << 3) /* Time Out Detected */
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#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
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#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
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#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
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#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
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#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
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#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
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#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
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#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
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#define FCR_ITL_1 (0)
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#define FCR_ITL_8 (FCR_ITL1)
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#define FCR_ITL_16 (FCR_ITL2)
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#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
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#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define LCR_SB (1 << 6) /* Set Break */
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#define LCR_STKYP (1 << 5) /* Sticky Parity */
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#define LCR_EPS (1 << 4) /* Even Parity Select */
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#define LCR_PEN (1 << 3) /* Parity Enable */
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#define LCR_STB (1 << 2) /* Stop Bit */
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#define LCR_WLS1 (1 << 1) /* Word Length Select */
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#define LCR_WLS0 (1 << 0) /* Word Length Select */
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#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
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#define LSR_TEMT (1 << 6) /* Transmitter Empty */
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#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
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#define LSR_BI (1 << 4) /* Break Interrupt */
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#define LSR_FE (1 << 3) /* Framing Error */
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#define LSR_PE (1 << 2) /* Parity Error */
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#define MCR_LOOP (1 << 4)
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#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
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#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
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#define MCR_RTS (1 << 1) /* Request to Send */
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#define MCR_DTR (1 << 0) /* Data Terminal Ready */
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#define MSR_DCD (1 << 7) /* Data Carrier Detect */
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#define MSR_RI (1 << 6) /* Ring Indicator */
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#define MSR_DSR (1 << 5) /* Data Set Ready */
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#define MSR_CTS (1 << 4) /* Clear To Send */
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#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
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#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
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#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
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#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
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/*
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* IrSR (Infrared Selection Register)
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*/
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#define STISR_RXPL (1 << 4) /* Receive Data Polarity */
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#define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
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#define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
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#define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
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#define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
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#endif /* __ASM_ARCH_REGS_UART_H */
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