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e8e523a42a
'commit 2637e5fd23 ("i2c: octeon: Fix i2c fail problem when a process is
terminated by a signal")' removed the wait_event_interruptible_timeout to
prevent half/mixed i2c messages from being sent/recievd but forgot to
drop the signal handling case in the return handling. This just removes
this dead code. While at it the return variable is adjusted to the type
expected.
Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
634 lines
15 KiB
C
634 lines
15 KiB
C
/*
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* (C) Copyright 2009-2010
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* Nokia Siemens Networks, michael.lawnick.ext@nsn.com
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*
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* Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
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*
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* This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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#define DRV_NAME "i2c-octeon"
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/* The previous out-of-tree version was implicitly version 1.0. */
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#define DRV_VERSION "2.0"
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/* register offsets */
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#define SW_TWSI 0x00
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#define TWSI_INT 0x10
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/* Controller command patterns */
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#define SW_TWSI_V 0x8000000000000000ull
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#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
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#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
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#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
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#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
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#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
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#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
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#define SW_TWSI_R 0x0100000000000000ull
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/* Controller command and status bits */
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#define TWSI_CTL_CE 0x80
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#define TWSI_CTL_ENAB 0x40
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#define TWSI_CTL_STA 0x20
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#define TWSI_CTL_STP 0x10
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#define TWSI_CTL_IFLG 0x08
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#define TWSI_CTL_AAK 0x04
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/* Some status values */
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#define STAT_START 0x08
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#define STAT_RSTART 0x10
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#define STAT_TXADDR_ACK 0x18
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#define STAT_TXDATA_ACK 0x28
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#define STAT_RXADDR_ACK 0x40
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#define STAT_RXDATA_ACK 0x50
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#define STAT_IDLE 0xF8
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struct octeon_i2c {
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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u32 twsi_freq;
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int sys_freq;
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resource_size_t twsi_phys;
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void __iomem *twsi_base;
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resource_size_t regsize;
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struct device *dev;
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};
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/**
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* octeon_i2c_write_sw - write an I2C core register.
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* @i2c: The struct octeon_i2c.
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* @eop_reg: Register selector.
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* @data: Value to be written.
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
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u64 eop_reg,
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u8 data)
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{
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u64 tmp;
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__raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
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} while ((tmp & SW_TWSI_V) != 0);
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}
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/**
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* octeon_i2c_read_sw - write an I2C core register.
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* @i2c: The struct octeon_i2c.
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* @eop_reg: Register selector.
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*
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* Returns the data.
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*
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* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
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*/
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static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
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{
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u64 tmp;
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__raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
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do {
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tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
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} while ((tmp & SW_TWSI_V) != 0);
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return tmp & 0xFF;
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}
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/**
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* octeon_i2c_write_int - write the TWSI_INT register
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* @i2c: The struct octeon_i2c.
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* @data: Value to be written.
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*/
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static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
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{
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__raw_writeq(data, i2c->twsi_base + TWSI_INT);
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__raw_readq(i2c->twsi_base + TWSI_INT);
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}
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/**
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* octeon_i2c_int_enable - enable the TS interrupt.
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* @i2c: The struct octeon_i2c.
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*
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* The interrupt will be asserted when there is non-STAT_IDLE state in
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* the SW_TWSI_EOP_TWSI_STAT register.
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*/
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static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, 0x40);
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}
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/**
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* octeon_i2c_int_disable - disable the TS interrupt.
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* @i2c: The struct octeon_i2c.
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*/
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static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
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{
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octeon_i2c_write_int(i2c, 0);
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}
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/**
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* octeon_i2c_unblock - unblock the bus.
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* @i2c: The struct octeon_i2c.
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*
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* If there was a reset while a device was driving 0 to bus,
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* bus is blocked. We toggle it free manually by some clock
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* cycles and send a stop.
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*/
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static void octeon_i2c_unblock(struct octeon_i2c *i2c)
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{
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int i;
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dev_dbg(i2c->dev, "%s\n", __func__);
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for (i = 0; i < 9; i++) {
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octeon_i2c_write_int(i2c, 0x0);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x200);
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udelay(5);
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}
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octeon_i2c_write_int(i2c, 0x300);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x100);
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udelay(5);
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octeon_i2c_write_int(i2c, 0x0);
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}
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/**
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* octeon_i2c_isr - the interrupt service routine.
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* @int: The irq, unused.
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* @dev_id: Our struct octeon_i2c.
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*/
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static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
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{
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struct octeon_i2c *i2c = dev_id;
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octeon_i2c_int_disable(i2c);
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wake_up(&i2c->queue);
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return IRQ_HANDLED;
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}
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static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
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{
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return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
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}
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/**
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* octeon_i2c_wait - wait for the IFLG to be set.
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* @i2c: The struct octeon_i2c.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_wait(struct octeon_i2c *i2c)
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{
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long result;
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octeon_i2c_int_enable(i2c);
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result = wait_event_timeout(i2c->queue,
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octeon_i2c_test_iflg(i2c),
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i2c->adap.timeout);
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octeon_i2c_int_disable(i2c);
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if (result == 0) {
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dev_dbg(i2c->dev, "%s: timeout\n", __func__);
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return -ETIMEDOUT;
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}
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return 0;
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}
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/**
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* octeon_i2c_start - send START to the bus.
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* @i2c: The struct octeon_i2c.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_start(struct octeon_i2c *i2c)
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{
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u8 data;
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int result;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STA);
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result = octeon_i2c_wait(i2c);
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if (result) {
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if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
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/*
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* Controller refused to send start flag May
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* be a client is holding SDA low - let's try
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* to free it.
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*/
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octeon_i2c_unblock(i2c);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STA);
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result = octeon_i2c_wait(i2c);
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}
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if (result)
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return result;
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}
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data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if ((data != STAT_START) && (data != STAT_RSTART)) {
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dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
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return -EIO;
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}
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return 0;
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}
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/**
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* octeon_i2c_stop - send STOP to the bus.
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* @i2c: The struct octeon_i2c.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_stop(struct octeon_i2c *i2c)
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{
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u8 data;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_STP);
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data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if (data != STAT_IDLE) {
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dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
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return -EIO;
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}
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return 0;
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}
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/**
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* octeon_i2c_write - send data to the bus.
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* @i2c: The struct octeon_i2c.
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* @target: Target address.
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* @data: Pointer to the data to be sent.
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* @length: Length of the data.
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*
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* The address is sent over the bus, then the data.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
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const u8 *data, int length)
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{
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int i, result;
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u8 tmp;
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result = octeon_i2c_start(i2c);
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if (result)
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return result;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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for (i = 0; i < length; i++) {
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tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
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dev_err(i2c->dev,
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"%s: bad status before write (0x%x)\n",
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__func__, tmp);
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return -EIO;
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}
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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}
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return 0;
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}
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/**
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* octeon_i2c_read - receive data from the bus.
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* @i2c: The struct octeon_i2c.
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* @target: Target address.
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* @data: Pointer to the location to store the datae .
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* @length: Length of the data.
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*
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* The address is sent over the bus, then the data is read.
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*
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* Returns 0 on success, otherwise a negative errno.
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*/
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static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
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u8 *data, int length)
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{
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int i, result;
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u8 tmp;
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if (length < 1)
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return -EINVAL;
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result = octeon_i2c_start(i2c);
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if (result)
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return result;
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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for (i = 0; i < length; i++) {
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tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
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if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
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dev_err(i2c->dev,
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"%s: bad status before read (0x%x)\n",
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__func__, tmp);
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return -EIO;
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}
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if (i+1 < length)
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB | TWSI_CTL_AAK);
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else
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octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
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TWSI_CTL_ENAB);
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result = octeon_i2c_wait(i2c);
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if (result)
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return result;
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data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
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}
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return 0;
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}
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/**
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* octeon_i2c_xfer - The driver's master_xfer function.
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* @adap: Pointer to the i2c_adapter structure.
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* @msgs: Pointer to the messages to be processed.
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* @num: Length of the MSGS array.
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*
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* Returns the number of messages processed, or a negative errno on
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* failure.
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*/
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static int octeon_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs,
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int num)
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{
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struct i2c_msg *pmsg;
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int i;
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int ret = 0;
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struct octeon_i2c *i2c = i2c_get_adapdata(adap);
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for (i = 0; ret == 0 && i < num; i++) {
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pmsg = &msgs[i];
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dev_dbg(i2c->dev,
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"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
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pmsg->flags & I2C_M_RD ? "read" : "write",
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pmsg->len, pmsg->addr, i + 1, num);
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if (pmsg->flags & I2C_M_RD)
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ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
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pmsg->len);
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else
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ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
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pmsg->len);
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}
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octeon_i2c_stop(i2c);
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return (ret != 0) ? ret : num;
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}
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static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm octeon_i2c_algo = {
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.master_xfer = octeon_i2c_xfer,
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.functionality = octeon_i2c_functionality,
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};
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static struct i2c_adapter octeon_i2c_ops = {
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.owner = THIS_MODULE,
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.name = "OCTEON adapter",
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.algo = &octeon_i2c_algo,
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.timeout = HZ / 50,
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};
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/**
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* octeon_i2c_setclock - Calculate and set clock divisors.
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*/
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static int octeon_i2c_setclock(struct octeon_i2c *i2c)
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{
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int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
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int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
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for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
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/*
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* An mdiv value of less than 2 seems to not work well
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* with ds1337 RTCs, so we constrain it to larger
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* values.
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*/
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for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
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/*
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* For given ndiv and mdiv values check the
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* two closest thp values.
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*/
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tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
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tclk *= (1 << ndiv_idx);
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thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
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for (inc = 0; inc <= 1; inc++) {
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thp_idx = thp_base + inc;
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if (thp_idx < 5 || thp_idx > 0xff)
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continue;
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|
|
|
foscl = i2c->sys_freq / (2 * (thp_idx + 1));
|
|
foscl = foscl / (1 << ndiv_idx);
|
|
foscl = foscl / (mdiv_idx + 1) / 10;
|
|
diff = abs(foscl - i2c->twsi_freq);
|
|
if (diff < delta_hz) {
|
|
delta_hz = diff;
|
|
thp = thp_idx;
|
|
mdiv = mdiv_idx;
|
|
ndiv = ndiv_idx;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
|
|
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
|
|
{
|
|
u8 status;
|
|
int tries;
|
|
|
|
/* disable high level controller, enable bus access */
|
|
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
|
|
|
|
/* reset controller */
|
|
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
|
|
|
|
for (tries = 10; tries; tries--) {
|
|
udelay(1);
|
|
status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
|
|
if (status == STAT_IDLE)
|
|
return 0;
|
|
}
|
|
dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
|
|
return -EIO;
|
|
}
|
|
|
|
static int octeon_i2c_probe(struct platform_device *pdev)
|
|
{
|
|
int irq, result = 0;
|
|
struct octeon_i2c *i2c;
|
|
struct resource *res_mem;
|
|
|
|
/* All adaptors have an irq. */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
|
|
if (!i2c) {
|
|
dev_err(&pdev->dev, "kzalloc failed\n");
|
|
result = -ENOMEM;
|
|
goto out;
|
|
}
|
|
i2c->dev = &pdev->dev;
|
|
|
|
res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (res_mem == NULL) {
|
|
dev_err(i2c->dev, "found no memory resource\n");
|
|
result = -ENXIO;
|
|
goto out;
|
|
}
|
|
i2c->twsi_phys = res_mem->start;
|
|
i2c->regsize = resource_size(res_mem);
|
|
|
|
/*
|
|
* "clock-rate" is a legacy binding, the official binding is
|
|
* "clock-frequency". Try the official one first and then
|
|
* fall back if it doesn't exist.
|
|
*/
|
|
if (of_property_read_u32(pdev->dev.of_node,
|
|
"clock-frequency", &i2c->twsi_freq) &&
|
|
of_property_read_u32(pdev->dev.of_node,
|
|
"clock-rate", &i2c->twsi_freq)) {
|
|
dev_err(i2c->dev,
|
|
"no I2C 'clock-rate' or 'clock-frequency' property\n");
|
|
result = -ENXIO;
|
|
goto out;
|
|
}
|
|
|
|
i2c->sys_freq = octeon_get_io_clock_rate();
|
|
|
|
if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
|
|
res_mem->name)) {
|
|
dev_err(i2c->dev, "request_mem_region failed\n");
|
|
goto out;
|
|
}
|
|
i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
|
|
|
|
init_waitqueue_head(&i2c->queue);
|
|
|
|
i2c->irq = irq;
|
|
|
|
result = devm_request_irq(&pdev->dev, i2c->irq,
|
|
octeon_i2c_isr, 0, DRV_NAME, i2c);
|
|
if (result < 0) {
|
|
dev_err(i2c->dev, "failed to attach interrupt\n");
|
|
goto out;
|
|
}
|
|
|
|
result = octeon_i2c_initlowlevel(i2c);
|
|
if (result) {
|
|
dev_err(i2c->dev, "init low level failed\n");
|
|
goto out;
|
|
}
|
|
|
|
result = octeon_i2c_setclock(i2c);
|
|
if (result) {
|
|
dev_err(i2c->dev, "clock init failed\n");
|
|
goto out;
|
|
}
|
|
|
|
i2c->adap = octeon_i2c_ops;
|
|
i2c->adap.dev.parent = &pdev->dev;
|
|
i2c->adap.dev.of_node = pdev->dev.of_node;
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
|
platform_set_drvdata(pdev, i2c);
|
|
|
|
result = i2c_add_adapter(&i2c->adap);
|
|
if (result < 0) {
|
|
dev_err(i2c->dev, "failed to add adapter\n");
|
|
goto out;
|
|
}
|
|
dev_info(i2c->dev, "version %s\n", DRV_VERSION);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
return result;
|
|
};
|
|
|
|
static int octeon_i2c_remove(struct platform_device *pdev)
|
|
{
|
|
struct octeon_i2c *i2c = platform_get_drvdata(pdev);
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
|
return 0;
|
|
};
|
|
|
|
static struct of_device_id octeon_i2c_match[] = {
|
|
{
|
|
.compatible = "cavium,octeon-3860-twsi",
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, octeon_i2c_match);
|
|
|
|
static struct platform_driver octeon_i2c_driver = {
|
|
.probe = octeon_i2c_probe,
|
|
.remove = octeon_i2c_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = octeon_i2c_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(octeon_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
|
|
MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION(DRV_VERSION);
|