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1764c3edc6
Commit7c78f67e9b("arm64: enable tlbi range instructions") breaks LLVM's integrated assembler, because -Wa,-march is only passed to external assemblers and therefore, the new instructions are not enabled when IAS is used. This change adds a common architecture version preamble, which can be used in inline assembly blocks that contain instructions that require a newer architecture version, and uses it to fix __TLBI_0 and __TLBI_1 with ARM64_TLB_RANGE. Fixes:7c78f67e9b("arm64: enable tlbi range instructions") Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Tested-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://github.com/ClangBuiltLinux/linux/issues/1106 Link: https://lore.kernel.org/r/20200827203608.1225689-1-samitolvanen@google.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
27 lines
850 B
C
27 lines
850 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_COMPILER_H
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#define __ASM_COMPILER_H
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#ifdef ARM64_ASM_ARCH
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#define ARM64_ASM_PREAMBLE ".arch " ARM64_ASM_ARCH "\n"
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#else
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#define ARM64_ASM_PREAMBLE
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#endif
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/*
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* The EL0/EL1 pointer bits used by a pointer authentication code.
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* This is dependent on TBI0/TBI1 being enabled, or bits 63:56 would also apply.
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*/
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#define ptrauth_user_pac_mask() GENMASK_ULL(54, vabits_actual)
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#define ptrauth_kernel_pac_mask() GENMASK_ULL(63, vabits_actual)
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/* Valid for EL0 TTBR0 and EL1 TTBR1 instruction pointers */
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#define ptrauth_clear_pac(ptr) \
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((ptr & BIT_ULL(55)) ? (ptr | ptrauth_kernel_pac_mask()) : \
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(ptr & ~ptrauth_user_pac_mask()))
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#define __builtin_return_address(val) \
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(void *)(ptrauth_clear_pac((unsigned long)__builtin_return_address(val)))
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#endif /* __ASM_COMPILER_H */
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