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Ignoring the last page when ddr size is 128M. Cached accesses to last page is causing the processor to prefetch using address above 128M stepping out of the DDR address space. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/981/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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| gpio.c | ||
| irq.c | ||
| Makefile | ||
| prom.c | ||
| serial.c | ||
| setup.c | ||
| time.c | ||
| wgt634u.c | ||