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28c80aa707
This patch adds clock types into platform data to support external clock divider instead of internal clock divider. It is defined that what kinds of clock type is used in machine. Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
147 lines
3.8 KiB
C
147 lines
3.8 KiB
C
/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/serial_core.h>
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#include <linux/gpio.h>
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#include <linux/mmc/host.h>
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#include <linux/platform_device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <plat/regs-serial.h>
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#include <plat/s5pv310.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/sdhci.h>
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#include <mach/map.h>
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/* Following are default values for UCON, ULCON and UFCON UART registers */
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#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI | \
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S3C2443_UCON_RXERR_IRQEN)
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#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
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#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S5PV210_UFCON_TXTRIG4 | \
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S5PV210_UFCON_RXTRIG4)
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static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = SMDKC210_UCON_DEFAULT,
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.ulcon = SMDKC210_ULCON_DEFAULT,
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.ufcon = SMDKC210_UFCON_DEFAULT,
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},
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[1] = {
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.hwport = 1,
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.flags = 0,
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.ucon = SMDKC210_UCON_DEFAULT,
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.ulcon = SMDKC210_ULCON_DEFAULT,
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.ufcon = SMDKC210_UFCON_DEFAULT,
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},
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[2] = {
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.hwport = 2,
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.flags = 0,
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.ucon = SMDKC210_UCON_DEFAULT,
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.ulcon = SMDKC210_ULCON_DEFAULT,
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.ufcon = SMDKC210_UFCON_DEFAULT,
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},
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[3] = {
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.hwport = 3,
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.flags = 0,
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.ucon = SMDKC210_UCON_DEFAULT,
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.ulcon = SMDKC210_ULCON_DEFAULT,
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.ufcon = SMDKC210_UFCON_DEFAULT,
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},
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};
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static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = S5PV310_GPK0(2),
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.ext_cd_gpio_invert = 1,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
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.max_width = 8,
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.host_caps = MMC_CAP_8_BIT_DATA,
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#endif
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};
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static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = S5PV310_GPK0(2),
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.ext_cd_gpio_invert = 1,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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};
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static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = S5PV310_GPK2(2),
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.ext_cd_gpio_invert = 1,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
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.max_width = 8,
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.host_caps = MMC_CAP_8_BIT_DATA,
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#endif
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};
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static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
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.cd_type = S3C_SDHCI_CD_GPIO,
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.ext_cd_gpio = S5PV310_GPK2(2),
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.ext_cd_gpio_invert = 1,
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.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
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};
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static struct platform_device *smdkc210_devices[] __initdata = {
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&s3c_device_hsmmc0,
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&s3c_device_hsmmc1,
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&s3c_device_hsmmc2,
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&s3c_device_hsmmc3,
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&s3c_device_rtc,
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&s3c_device_wdt,
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};
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static void __init smdkc210_map_io(void)
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{
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s5p_init_io(NULL, 0, S5P_VA_CHIPID);
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s3c24xx_init_clocks(24000000);
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s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
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}
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static void __init smdkc210_machine_init(void)
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{
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s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
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s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
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s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
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s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
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#ifdef CONFIG_CACHE_L2X0
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l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
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#endif
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platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
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}
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MACHINE_START(SMDKC210, "SMDKC210")
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/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
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.boot_params = S5P_PA_SDRAM + 0x100,
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.init_irq = s5pv310_init_irq,
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.map_io = smdkc210_map_io,
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.init_machine = smdkc210_machine_init,
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.timer = &s5pv310_timer,
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MACHINE_END
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