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82ab97c8c7
The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> |
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cec | ||
common | ||
dvb-core | ||
dvb-frontends | ||
firewire | ||
i2c | ||
mc | ||
mmc | ||
pci | ||
platform | ||
radio | ||
rc | ||
spi | ||
test-drivers | ||
tuners | ||
usb | ||
v4l2-core | ||
Kconfig | ||
Makefile |