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effbc4fd8e
Daniel Vetter wrote First pull request for 3.5-next, slightly large than usual because new things kept coming in since the last pull for 3.4. Highlights: - first batch of hw enablement for vlv (Jesse et al) and hsw (Eugeni). pci ids are not yet added, and there's still quite a few patches to merge (mostly modesetting). To make QA easier I've decided to merge this stuff in pieces. - loads of cleanups and prep patches spurred by the above. Especially vlv is a real frankenstein chip, but also hsw is stretching our driver's code design. Expect more to come in this area for 3.5. - more gmbus fixes, cleanups and improvements by Daniel Kurtz. Again, there are more patches needed (and some already queued up), but I wanted to split this a bit for better testing. - pwrite/pread rework and retuning. This series has been in the works for a few months already and a lot of i-g-t tests have been created for it. Now it's finally ready to be merged. Note that one patch in this series touches include/pagemap.h, that patch is acked-by akpm. - reduce mappable pressure and relocation throughput improvements from Chris. - mmap offset exhaustion mitigation by Chris Wilson. - a start at figuring out which codepaths in our messy dri1/ums+gem/kms driver we actually need to support by bailing out of unsupported case. The driver now refuses to load without kms on gen6+ and disallows a few ioctls that userspace never used in certain cases. More of this will definitely come. - More decoupling of global gtt and ppgtt. - Improved dual-link lvds detection by Takashi Iwai. - Shut up the compiler + plus fix the fallout (Ben) - Inverted panel brightness handling (mostly Acer manages to break things in this way). - Small fixlets and adjustements and some minor things to help debugging. Regression-wise QA reported quite a few issues on ivb, but all of them turned out to be hw stability issues which are already fixed in drm-intel-fixes (QA runs the nightly regression tests on -next alone, without -fixes automatically merged in). There's still one issue open on snb, it looks like occlusion query writes are not quite as cache coherent as we've expected. With some of the pwrite adjustements we can now reliably hit this. Kernel workaround for it is in the works." * 'drm-intel-next' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits) drm/i915: VCS is not the last ring drm/i915: Add a dual link lvds quirk for MacBook Pro 8,2 drm/i915: make quirks more verbose drm/i915: dump the DMA fetch addr register on pre-gen6 drm/i915/sdvo: Include YRPB as an additional TV output type drm/i915: disallow gem init ioctl on ilk drm/i915: refuse to load on gen6+ without kms drm/i915: extract gt interrupt handler drm/i915: use render gen to switch ring irq functions drm/i915: rip out old HWSTAM missed irq WA for vlv drm/i915: open code gen6+ ring irqs drm/i915: ring irq cleanups drm/i915: add SFUSE_STRAP registers for digital port detection drm/i915: add WM_LINETIME registers drm/i915: add WRPLL clocks drm/i915: add LCPLL control registers drm/i915: add SSC offsets for SBI access drm/i915: add port clock selection support for HSW drm/i915: add S PLL control drm/i915: add PIXCLK_GATE register ... Conflicts: drivers/char/agp/intel-agp.h drivers/char/agp/intel-gtt.c drivers/gpu/drm/i915/i915_debugfs.c
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/**************************************************************************
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*
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* Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
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*/
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#include <linux/export.h>
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#include "drmP.h"
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#if defined(CONFIG_X86)
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static void
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drm_clflush_page(struct page *page)
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{
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uint8_t *page_virtual;
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unsigned int i;
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if (unlikely(page == NULL))
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return;
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page_virtual = kmap_atomic(page);
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for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
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clflush(page_virtual + i);
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kunmap_atomic(page_virtual);
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}
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static void drm_cache_flush_clflush(struct page *pages[],
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unsigned long num_pages)
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{
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unsigned long i;
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mb();
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for (i = 0; i < num_pages; i++)
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drm_clflush_page(*pages++);
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mb();
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}
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static void
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drm_clflush_ipi_handler(void *null)
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{
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wbinvd();
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}
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#endif
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void
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drm_clflush_pages(struct page *pages[], unsigned long num_pages)
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{
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#if defined(CONFIG_X86)
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if (cpu_has_clflush) {
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drm_cache_flush_clflush(pages, num_pages);
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return;
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}
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if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
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printk(KERN_ERR "Timed out waiting for cache flush.\n");
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#elif defined(__powerpc__)
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unsigned long i;
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for (i = 0; i < num_pages; i++) {
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struct page *page = pages[i];
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void *page_virtual;
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if (unlikely(page == NULL))
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continue;
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page_virtual = kmap_atomic(page);
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flush_dcache_range((unsigned long)page_virtual,
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(unsigned long)page_virtual + PAGE_SIZE);
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kunmap_atomic(page_virtual);
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}
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#else
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printk(KERN_ERR "Architecture has no drm_cache.c support\n");
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WARN_ON_ONCE(1);
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#endif
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}
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EXPORT_SYMBOL(drm_clflush_pages);
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void
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drm_clflush_virt_range(char *addr, unsigned long length)
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{
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#if defined(CONFIG_X86)
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if (cpu_has_clflush) {
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char *end = addr + length;
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mb();
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for (; addr < end; addr += boot_cpu_data.x86_clflush_size)
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clflush(addr);
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clflush(end - 1);
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mb();
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return;
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}
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if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0)
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printk(KERN_ERR "Timed out waiting for cache flush.\n");
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#else
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printk(KERN_ERR "Architecture has no drm_cache.c support\n");
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WARN_ON_ONCE(1);
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#endif
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}
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EXPORT_SYMBOL(drm_clflush_virt_range);
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