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The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading its current value from the NS register. Using the pre-divider wasn't really intended when creating these ops. The pixel RCG was only intended to achieve fractional multiplication provided in the pixel_table array. Leaving the pre-divider to the existing register value results in a wrong pixel clock when the bootloader sets up the display. This was left unidentified because the IFC6410 Plus board on which this was verified didn't have a bootloader that configured the display. Don't set the RCG pre-divider in freq_tbl to the existing NS register value. Force it to 1 and only use the M/N counter to achieve the desired fractional multiplication. Cc: Vinay Simha <vinaysimha@inforcecomputing.com> Signed-off-by: Archit Taneja <architt@codeaurora.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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.. | ||
clk-alpha-pll.c | ||
clk-alpha-pll.h | ||
clk-branch.c | ||
clk-branch.h | ||
clk-pll.c | ||
clk-pll.h | ||
clk-rcg2.c | ||
clk-rcg.c | ||
clk-rcg.h | ||
clk-regmap-divider.c | ||
clk-regmap-divider.h | ||
clk-regmap-mux.c | ||
clk-regmap-mux.h | ||
clk-regmap.c | ||
clk-regmap.h | ||
common.c | ||
common.h | ||
gcc-apq8084.c | ||
gcc-ipq806x.c | ||
gcc-ipq4019.c | ||
gcc-msm8660.c | ||
gcc-msm8916.c | ||
gcc-msm8960.c | ||
gcc-msm8974.c | ||
gcc-msm8996.c | ||
gdsc.c | ||
gdsc.h | ||
Kconfig | ||
lcc-ipq806x.c | ||
lcc-msm8960.c | ||
Makefile | ||
mmcc-apq8084.c | ||
mmcc-msm8960.c | ||
mmcc-msm8974.c | ||
mmcc-msm8996.c | ||
reset.c | ||
reset.h |